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intel/compiler: Fix instruction size written calculation

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We are always aligning to REG_SIZE but when we have payload sources less
than REG_SIZE, size written is miscalculated.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
This commit is contained in:
Sagar Ghuge
2021-10-13 11:14:43 -07:00
parent be2bfe5fe8
commit 75c73fcdc4
1 changed files with 2 additions and 3 deletions
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5
src/intel/compiler/brw_fs_builder.h
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@@ -771,9 +771,8 @@ namespace brw {
inst->header_size = header_size; inst->header_size = header_size;
inst->size_written = header_size * REG_SIZE; inst->size_written = header_size * REG_SIZE;
for (unsigned i = header_size; i < sources; i++) { for (unsigned i = header_size; i < sources; i++) {
inst->size_written += inst->size_written += dispatch_width() * type_sz(src[i].type) *
ALIGN(dispatch_width() * type_sz(src[i].type) * dst.stride, dst.stride;
REG_SIZE);
} }
return inst; return inst;