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intel/compiler: Mark some methods and parameters const

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Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
This commit is contained in:
Matt Turner
2016-09-23 15:15:33 +03:00
committed by Marge Bot
parent 03ac90aae5
commit 75a33e268e
8 changed files with 27 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/intel/compiler/brw_fs.cpp
View File

@@ -6959,13 +6959,13 @@ fs_visitor::lower_barycentrics()
}
void
fs_visitor::dump_instructions()
fs_visitor::dump_instructions() const
{
dump_instructions(NULL);
}
void
fs_visitor::dump_instructions(const char *name)
fs_visitor::dump_instructions(const char *name) const
{
FILE *file = stderr;
if (name && geteuid() != 0) {
@@ -6998,15 +6998,15 @@ fs_visitor::dump_instructions(const char *name)
}
void
fs_visitor::dump_instruction(backend_instruction *be_inst)
fs_visitor::dump_instruction(const backend_instruction *be_inst) const
{
dump_instruction(be_inst, stderr);
}
void
fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
fs_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) const
{
fs_inst *inst = (fs_inst *)be_inst;
const fs_inst *inst = (const fs_inst *)be_inst;
if (inst->predicate) {
fprintf(file, "(%cf%d.%d) ",

10
src/intel/compiler/brw_fs.h
View File

@@ -145,7 +145,7 @@ public:
bool assign_regs(bool allow_spilling, bool spill_all);
void assign_regs_trivial();
void calculate_payload_ranges(int payload_node_count,
int *payload_last_use_ip);
int *payload_last_use_ip) const;
void split_virtual_grfs();
bool compact_virtual_grfs();
void assign_constant_locations();
@@ -330,10 +330,10 @@ public:
fs_reg interp_reg(int location, int channel);
virtual void dump_instructions();
virtual void dump_instructions(const char *name);
void dump_instruction(backend_instruction *inst);
void dump_instruction(backend_instruction *inst, FILE *file);
virtual void dump_instructions() const;
virtual void dump_instructions(const char *name) const;
void dump_instruction(const backend_instruction *inst) const;
void dump_instruction(const backend_instruction *inst, FILE *file) const;
const brw_base_prog_key *const key;
const struct brw_sampler_prog_key_data *key_tex;

8
src/intel/compiler/brw_fs_reg_allocate.cpp
View File

@@ -331,7 +331,7 @@ count_to_loop_end(const bblock_t *block)
}
void fs_visitor::calculate_payload_ranges(int payload_node_count,
int *payload_last_use_ip)
int *payload_last_use_ip) const
{
int loop_depth = 0;
int loop_end_ip = 0;
@@ -444,7 +444,7 @@ public:
private:
void setup_live_interference(unsigned node,
int node_start_ip, int node_end_ip);
void setup_inst_interference(fs_inst *inst);
void setup_inst_interference(const fs_inst *inst);
void build_interference_graph(bool allow_spilling);
void discard_interference_graph();
@@ -490,7 +490,7 @@ private:
* contents.
*/
static void
get_used_mrfs(fs_visitor *v, bool *mrf_used)
get_used_mrfs(const fs_visitor *v, bool *mrf_used)
{
int reg_width = v->dispatch_width / 8;
@@ -599,7 +599,7 @@ fs_reg_alloc::setup_live_interference(unsigned node,
}
void
fs_reg_alloc::setup_inst_interference(fs_inst *inst)
fs_reg_alloc::setup_inst_interference(const fs_inst *inst)
{
/* Certain instructions can't safely use the same register for their
* sources and destination. Add interference.

2
src/intel/compiler/brw_ir_vec4.h
View File

@@ -285,7 +285,7 @@ public:
bool sol_final_write; /**< gen6: send commit message */
unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
bool is_send_from_grf();
bool is_send_from_grf() const;
unsigned size_read(unsigned arg) const;
bool can_reswizzle(const struct gen_device_info *devinfo, int dst_writemask,
int swizzle, int swizzle_mask);

4
src/intel/compiler/brw_shader.cpp
View File

@@ -1201,13 +1201,13 @@ backend_instruction::remove(bblock_t *block)
}
void
backend_shader::dump_instructions()
backend_shader::dump_instructions() const
{
dump_instructions(NULL);
}
void
backend_shader::dump_instructions(const char *name)
backend_shader::dump_instructions(const char *name) const
{
FILE *file = stderr;
if (name && geteuid() != 0) {

8
src/intel/compiler/brw_shader.h
View File

@@ -79,10 +79,10 @@ public:
brw::simple_allocator alloc;
virtual void dump_instruction(backend_instruction *inst) = 0;
virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
virtual void dump_instructions();
virtual void dump_instructions(const char *name);
virtual void dump_instruction(const backend_instruction *inst) const = 0;
virtual void dump_instruction(const backend_instruction *inst, FILE *file) const = 0;
virtual void dump_instructions() const;
virtual void dump_instructions(const char *name) const;
void calculate_cfg();

8
src/intel/compiler/brw_vec4.cpp
View File

@@ -147,7 +147,7 @@ dst_reg::equals(const dst_reg &r) const
}
bool
vec4_instruction::is_send_from_grf()
vec4_instruction::is_send_from_grf() const
{
switch (opcode) {
case SHADER_OPCODE_SHADER_TIME_ADD:
@@ -1605,15 +1605,15 @@ vec4_visitor::split_virtual_grfs()
}
void
vec4_visitor::dump_instruction(backend_instruction *be_inst)
vec4_visitor::dump_instruction(const backend_instruction *be_inst) const
{
dump_instruction(be_inst, stderr);
}
void
vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
vec4_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) const
{
vec4_instruction *inst = (vec4_instruction *)be_inst;
const vec4_instruction *inst = (const vec4_instruction *)be_inst;
if (inst->predicate) {
fprintf(file, "(%cf%d.%d%s) ",

4
src/intel/compiler/brw_vec4.h
View File

@@ -305,8 +305,8 @@ public:
src_reg get_timestamp();
void dump_instruction(backend_instruction *inst);
void dump_instruction(backend_instruction *inst, FILE *file);
void dump_instruction(const backend_instruction *inst) const;
void dump_instruction(const backend_instruction *inst, FILE *file) const;
bool is_high_sampler(src_reg sampler);