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radv: move common registers between VS/GS and NGG

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For more clarity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29031>
This commit is contained in:
Samuel Pitoiset
2024-05-08 11:53:42 +02:00
committed by Marge Bot
parent 69b0ee7b6c
commit 751e5d8bd7
3 changed files with 20 additions and 20 deletions
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12
src/amd/vulkan/radv_pipeline_graphics.c
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@@ -2818,9 +2818,9 @@ radv_emit_hw_vs(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs,
radeon_emit(cs, shader->config.rsrc1); radeon_emit(cs, shader->config.rsrc1);
radeon_emit(cs, shader->config.rsrc2); radeon_emit(cs, shader->config.rsrc2);
radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, shader->info.regs.vs.spi_vs_out_config); radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, shader->info.regs.spi_vs_out_config);
radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT, shader->info.regs.vs.spi_shader_pos_format); radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT, shader->info.regs.spi_shader_pos_format);
radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL, shader->info.regs.vs.pa_cl_vs_out_cntl); radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL, shader->info.regs.pa_cl_vs_out_cntl);
if (pdev->info.gfx_level <= GFX8) if (pdev->info.gfx_level <= GFX8)
radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF, shader->info.regs.vs.vgt_reuse_off); radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF, shader->info.regs.vs.vgt_reuse_off);
@@ -2832,7 +2832,7 @@ radv_emit_hw_vs(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs,
} }
if (pdev->info.gfx_level >= GFX10) { if (pdev->info.gfx_level >= GFX10) {
radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, shader->info.regs.vs.ge_pc_alloc); radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, shader->info.regs.ge_pc_alloc);
if (shader->info.stage == MESA_SHADER_TESS_EVAL) { if (shader->info.stage == MESA_SHADER_TESS_EVAL) {
radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, shader->info.regs.vgt_gs_onchip_cntl); radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, shader->info.regs.vgt_gs_onchip_cntl);
@@ -3214,10 +3214,10 @@ radv_emit_hw_gs(const struct radv_device *device, struct radeon_cmdbuf *ctx_cs,
radeon_emit(cs, gs->config.rsrc2); radeon_emit(cs, gs->config.rsrc2);
} }
radeon_set_sh_reg_idx(pdev, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, 3, gs->info.regs.gs.spi_shader_pgm_rsrc3_gs); radeon_set_sh_reg_idx(pdev, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, 3, gs->info.regs.spi_shader_pgm_rsrc3_gs);
if (pdev->info.gfx_level >= GFX10) { if (pdev->info.gfx_level >= GFX10) {
radeon_set_sh_reg_idx(pdev, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, 3, gs->info.regs.gs.spi_shader_pgm_rsrc4_gs); radeon_set_sh_reg_idx(pdev, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, 3, gs->info.regs.spi_shader_pgm_rsrc4_gs);
} }
} }

14
src/amd/vulkan/radv_shader.c
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@@ -1402,12 +1402,12 @@ radv_precompute_registers_hw_vs(struct radv_device *device, struct radv_shader_b
/* VS is required to export at least one param. */ /* VS is required to export at least one param. */
const uint32_t nparams = MAX2(info->outinfo.param_exports, 1); const uint32_t nparams = MAX2(info->outinfo.param_exports, 1);
info->regs.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1); info->regs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
if (pdev->info.gfx_level >= GFX10) { if (pdev->info.gfx_level >= GFX10) {
info->regs.vs.spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(info->outinfo.param_exports == 0); info->regs.spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(info->outinfo.param_exports == 0);
} }
info->regs.vs.spi_shader_pos_format = info->regs.spi_shader_pos_format =
S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
S_02870C_POS1_EXPORT_FORMAT(info->outinfo.pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP S_02870C_POS1_EXPORT_FORMAT(info->outinfo.pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
: V_02870C_SPI_SHADER_NONE) | : V_02870C_SPI_SHADER_NONE) |
@@ -1421,7 +1421,7 @@ radv_precompute_registers_hw_vs(struct radv_device *device, struct radv_shader_b
const unsigned cull_dist_mask = info->outinfo.cull_dist_mask; const unsigned cull_dist_mask = info->outinfo.cull_dist_mask;
const unsigned total_mask = clip_dist_mask | cull_dist_mask; const unsigned total_mask = clip_dist_mask | cull_dist_mask;
info->regs.vs.pa_cl_vs_out_cntl = info->regs.pa_cl_vs_out_cntl =
S_02881C_USE_VTX_POINT_SIZE(info->outinfo.writes_pointsize) | S_02881C_USE_VTX_POINT_SIZE(info->outinfo.writes_pointsize) |
S_02881C_USE_VTX_RENDER_TARGET_INDX(info->outinfo.writes_layer) | S_02881C_USE_VTX_RENDER_TARGET_INDX(info->outinfo.writes_layer) |
S_02881C_USE_VTX_VIEWPORT_INDX(info->outinfo.writes_viewport_index) | S_02881C_USE_VTX_VIEWPORT_INDX(info->outinfo.writes_viewport_index) |
@@ -1447,7 +1447,7 @@ radv_precompute_registers_hw_vs(struct radv_device *device, struct radv_shader_b
if (pdev->info.gfx_level >= GFX10) { if (pdev->info.gfx_level >= GFX10) {
const uint32_t oversub_pc_lines = late_alloc_wave64 ? pdev->info.pc_lines / 4 : 0; const uint32_t oversub_pc_lines = late_alloc_wave64 ? pdev->info.pc_lines / 4 : 0;
info->regs.vs.ge_pc_alloc = info->regs.ge_pc_alloc =
S_030980_OVERSUB_EN(oversub_pc_lines > 0) | S_030980_NUM_PC_LINES(oversub_pc_lines - 1); S_030980_OVERSUB_EN(oversub_pc_lines > 0) | S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
/* Required programming for tessellation (legacy pipeline only). */ /* Required programming for tessellation (legacy pipeline only). */
@@ -1500,11 +1500,11 @@ radv_precompute_registers_hw_gs(struct radv_device *device, struct radv_shader_b
info->regs.gs.vgt_gs_instance_cnt = info->regs.gs.vgt_gs_instance_cnt =
S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0); S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0);
info->regs.gs.spi_shader_pgm_rsrc3_gs = info->regs.spi_shader_pgm_rsrc3_gs =
ac_apply_cu_en(S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F), C_00B21C_CU_EN, 0, &pdev->info); ac_apply_cu_en(S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F), C_00B21C_CU_EN, 0, &pdev->info);
if (pdev->info.gfx_level >= GFX10) { if (pdev->info.gfx_level >= GFX10) {
info->regs.gs.spi_shader_pgm_rsrc4_gs = info->regs.spi_shader_pgm_rsrc4_gs =
ac_apply_cu_en(S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0), C_00B204_CU_EN_GFX10, ac_apply_cu_en(S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0), C_00B204_CU_EN_GFX10,
16, &pdev->info); 16, &pdev->info);
} }

14
src/amd/vulkan/radv_shader_info.h
View File

@@ -253,19 +253,12 @@ struct radv_shader_info {
/* Precomputed register values. */ /* Precomputed register values. */
struct { struct {
struct { struct {
uint32_t ge_pc_alloc;
uint32_t pa_cl_vs_out_cntl;
uint32_t spi_shader_late_alloc_vs; uint32_t spi_shader_late_alloc_vs;
uint32_t spi_shader_pgm_rsrc3_vs; uint32_t spi_shader_pgm_rsrc3_vs;
uint32_t spi_shader_pos_format;
uint32_t spi_vs_out_config;
uint32_t vgt_gs_instance_cnt;
uint32_t vgt_reuse_off; uint32_t vgt_reuse_off;
} vs; } vs;
struct { struct {
uint32_t spi_shader_pgm_rsrc3_gs;
uint32_t spi_shader_pgm_rsrc4_gs;
uint32_t vgt_esgs_ring_itemsize; uint32_t vgt_esgs_ring_itemsize;
uint32_t vgt_gs_instance_cnt; uint32_t vgt_gs_instance_cnt;
uint32_t vgt_gs_max_prims_per_subgroup; uint32_t vgt_gs_max_prims_per_subgroup;
@@ -296,6 +289,13 @@ struct radv_shader_info {
/* Common registers between stages. */ /* Common registers between stages. */
uint32_t vgt_gs_max_vert_out; uint32_t vgt_gs_max_vert_out;
uint32_t vgt_gs_onchip_cntl; uint32_t vgt_gs_onchip_cntl;
uint32_t spi_shader_pgm_rsrc3_gs;
uint32_t spi_shader_pgm_rsrc4_gs;
uint32_t ge_pc_alloc;
uint32_t pa_cl_vs_out_cntl;
uint32_t spi_vs_out_config;
uint32_t spi_shader_pos_format;
uint32_t vgt_gs_instance_cnt;
} regs; } regs;
}; };