diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 78c0db5f3ad..b59dd5f598f 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -68,7 +68,7 @@ struct PACKED bcolor_entry {
    uint8_t ui8[4];
    int8_t si8[4];
    uint32_t rgb10a2;
-   uint32_t z24; /* also s8? */
+   uint32_t z24;
    uint16_t
       srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
    uint8_t __pad1[56];
@@ -80,10 +80,12 @@ struct PACKED bcolor_entry {
 
 static void
 setup_border_colors(struct fd_texture_stateobj *tex,
-                    struct bcolor_entry *entries)
+                    struct bcolor_entry *entries,
+                    struct fd_screen *screen)
 {
    unsigned i, j;
    STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
+   const bool has_z24uint_s8uint = screen->info->a6xx.has_z24uint_s8uint;
 
    for (i = 0; i < tex->num_samplers; i++) {
       struct bcolor_entry *e = &entries[i];
@@ -132,13 +134,14 @@ setup_border_colors(struct fd_texture_stateobj *tex,
           * to desc->swizzle and desc->channel, the .x/.w component
           * is NONE and the stencil value is in the y component.
           * Meanwhile the hardware wants this in the .x component
-          * for x24s8 and x32_s8x24.
+          * for x24s8 and x32_s8x24, or the .y component for x24s8 with the
+          * special Z24UINT_S8UINT format.
           */
          if ((format == PIPE_FORMAT_X24S8_UINT) ||
              (format == PIPE_FORMAT_X32_S8X24_UINT)) {
             if (j == 0) {
                c = 1;
-               cd = 0;
+               cd = (format == PIPE_FORMAT_X24S8_UINT && has_z24uint_s8uint) ? 1 : 0;
             } else {
                continue;
             }
@@ -231,9 +234,10 @@ emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring) assert_dt
 
    entries = ptr;
 
-   setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
+   setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0], ctx->screen);
    setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
-                       &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
+                       &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers],
+                       ctx->screen);
 
    OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR, 2);
    OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);