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amdgpu/winsys: remove amdgpu_cs_has_chaining

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Store this property in admgpu_cs instead of using a function.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11010>
This commit is contained in:
Pierre-Eric Pelloux-Prayer
2021-05-26 12:02:48 +02:00
committed by Marge Bot
parent 1bd64d8cfb
commit 74c67f2b72
2 changed files with 10 additions and 13 deletions
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18
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
View File

@@ -414,15 +414,9 @@ static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs)
cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_JPEG; cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_JPEG;
} }
static bool amdgpu_cs_has_chaining(struct amdgpu_cs *cs) static inline unsigned amdgpu_cs_epilog_dws(struct amdgpu_cs *cs)
{ {
return cs->ws->info.chip_class >= GFX7 && if (cs->has_chaining)
(cs->ring_type == RING_GFX || cs->ring_type == RING_COMPUTE);
}
static unsigned amdgpu_cs_epilog_dws(struct amdgpu_cs *cs)
{
if (amdgpu_cs_has_chaining(cs))
return 4; /* for chaining */ return 4; /* for chaining */
return 0; return 0;
@@ -721,7 +715,7 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws,
* is the largest power of two that fits into the size field of the * is the largest power of two that fits into the size field of the
* INDIRECT_BUFFER packet. * INDIRECT_BUFFER packet.
*/ */
if (amdgpu_cs_has_chaining(cs)) if (cs->has_chaining)
buffer_size = 4 * util_next_power_of_two(ib->max_ib_size); buffer_size = 4 * util_next_power_of_two(ib->max_ib_size);
else else
buffer_size = 4 * util_next_power_of_two(4 * ib->max_ib_size); buffer_size = 4 * util_next_power_of_two(4 * ib->max_ib_size);
@@ -803,7 +797,7 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
*/ */
ib_size = MAX2(ib_size, ib->max_check_space_size); ib_size = MAX2(ib_size, ib->max_check_space_size);
if (!amdgpu_cs_has_chaining(cs)) { if (!cs->has_chaining) {
ib_size = MAX2(ib_size, ib_size = MAX2(ib_size,
4 * MIN2(util_next_power_of_two(ib->max_ib_size), 4 * MIN2(util_next_power_of_two(ib->max_ib_size),
amdgpu_ib_max_submit_dwords(ib->ib_type))); amdgpu_ib_max_submit_dwords(ib->ib_type)));
@@ -997,6 +991,8 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs,
cs->ring_type = ring_type; cs->ring_type = ring_type;
cs->stop_exec_on_failure = stop_exec_on_failure; cs->stop_exec_on_failure = stop_exec_on_failure;
cs->noop = ctx->ws->noop_cs; cs->noop = ctx->ws->noop_cs;
cs->has_chaining = ctx->ws->info.chip_class >= GFX7 &&
(ring_type == RING_GFX || ring_type == RING_COMPUTE);
struct amdgpu_cs_fence_info fence_info; struct amdgpu_cs_fence_info fence_info;
fence_info.handle = cs->ctx->user_fence_bo; fence_info.handle = cs->ctx->user_fence_bo;
@@ -1154,7 +1150,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw,
return true; return true;
} }
if (!amdgpu_cs_has_chaining(cs)) { if (!cs->has_chaining) {
assert(!force_chaining); assert(!force_chaining);
return false; return false;
} }

1
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
View File

@@ -151,6 +151,7 @@ struct amdgpu_cs {
void *flush_data; void *flush_data;
bool stop_exec_on_failure; bool stop_exec_on_failure;
bool noop; bool noop;
bool has_chaining;
struct util_queue_fence flush_completed; struct util_queue_fence flush_completed;
struct pipe_fence_handle *next_fence; struct pipe_fence_handle *next_fence;