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amd/common/gfx10: add register JSON

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A small number of fields now need new disambiguation.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Nicolai Hähnle
2019-05-07 02:37:19 +02:00
committed by Marek Olšák
parent 536782b0b7
commit 74a26af913
11 changed files with 22383 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/amd/common/meson.build
View File

@@ -20,7 +20,8 @@
sid_tables_h = custom_target(
'sid_tables_h',
input : ['sid_tables.py', 'sid.h', '../registers/amdgfxregs.json', '../registers/pkt3.json'],
input : ['sid_tables.py', 'sid.h', '../registers/amdgfxregs.json', '../registers/pkt3.json',
'../registers/gfx10.json', '../registers/gfx10-rsrc.json'],
output : 'sid_tables.h',
command : [prog_python, '@INPUT@'],
capture : true,
@@ -28,7 +29,8 @@ sid_tables_h = custom_target(
amdgfxregs_h = custom_target(
'amdgfxregs_h',
input : ['../registers/makeregheader.py', '../registers/amdgfxregs.json', '../registers/pkt3.json'],
input : ['../registers/makeregheader.py', '../registers/amdgfxregs.json', '../registers/pkt3.json',
'../registers/gfx10.json', '../registers/gfx10-rsrc.json'],
output : 'amdgfxregs.h',
command : [prog_python, '@INPUT@', '--sort', 'address', '--guard', 'AMDGFXREGS_H'],
capture : true,

429
src/amd/registers/gfx10-rsrc.json Normal file
View File

@@ -0,0 +1,429 @@
{
"enums": {
"IMG_FORMAT": {
"entries": [
{"name": "IMG_FORMAT_INVALID", "value": 0},
{"name": "IMG_FORMAT_8_UNORM", "value": 1},
{"name": "IMG_FORMAT_8_SNORM", "value": 2},
{"name": "IMG_FORMAT_8_USCALED", "value": 3},
{"name": "IMG_FORMAT_8_SSCALED", "value": 4},
{"name": "IMG_FORMAT_8_UINT", "value": 5},
{"name": "IMG_FORMAT_8_SINT", "value": 6},
{"name": "IMG_FORMAT_16_UNORM", "value": 7},
{"name": "IMG_FORMAT_16_SNORM", "value": 8},
{"name": "IMG_FORMAT_16_USCALED", "value": 9},
{"name": "IMG_FORMAT_16_SSCALED", "value": 10},
{"name": "IMG_FORMAT_16_UINT", "value": 11},
{"name": "IMG_FORMAT_16_SINT", "value": 12},
{"name": "IMG_FORMAT_16_FLOAT", "value": 13},
{"name": "IMG_FORMAT_8_8_UNORM", "value": 14},
{"name": "IMG_FORMAT_8_8_SNORM", "value": 15},
{"name": "IMG_FORMAT_8_8_USCALED", "value": 16},
{"name": "IMG_FORMAT_8_8_SSCALED", "value": 17},
{"name": "IMG_FORMAT_8_8_UINT", "value": 18},
{"name": "IMG_FORMAT_8_8_SINT", "value": 19},
{"name": "IMG_FORMAT_32_UINT", "value": 20},
{"name": "IMG_FORMAT_32_SINT", "value": 21},
{"name": "IMG_FORMAT_32_FLOAT", "value": 22},
{"name": "IMG_FORMAT_16_16_UNORM", "value": 23},
{"name": "IMG_FORMAT_16_16_SNORM", "value": 24},
{"name": "IMG_FORMAT_16_16_USCALED", "value": 25},
{"name": "IMG_FORMAT_16_16_SSCALED", "value": 26},
{"name": "IMG_FORMAT_16_16_UINT", "value": 27},
{"name": "IMG_FORMAT_16_16_SINT", "value": 28},
{"name": "IMG_FORMAT_16_16_FLOAT", "value": 29},
{"name": "IMG_FORMAT_10_11_11_UNORM", "value": 30},
{"name": "IMG_FORMAT_10_11_11_SNORM", "value": 31},
{"name": "IMG_FORMAT_10_11_11_USCALED", "value": 32},
{"name": "IMG_FORMAT_10_11_11_SSCALED", "value": 33},
{"name": "IMG_FORMAT_10_11_11_UINT", "value": 34},
{"name": "IMG_FORMAT_10_11_11_SINT", "value": 35},
{"name": "IMG_FORMAT_10_11_11_FLOAT", "value": 36},
{"name": "IMG_FORMAT_11_11_10_UNORM", "value": 37},
{"name": "IMG_FORMAT_11_11_10_SNORM", "value": 38},
{"name": "IMG_FORMAT_11_11_10_USCALED", "value": 39},
{"name": "IMG_FORMAT_11_11_10_SSCALED", "value": 40},
{"name": "IMG_FORMAT_11_11_10_UINT", "value": 41},
{"name": "IMG_FORMAT_11_11_10_SINT", "value": 42},
{"name": "IMG_FORMAT_11_11_10_FLOAT", "value": 43},
{"name": "IMG_FORMAT_10_10_10_2_UNORM", "value": 44},
{"name": "IMG_FORMAT_10_10_10_2_SNORM", "value": 45},
{"name": "IMG_FORMAT_10_10_10_2_USCALED", "value": 46},
{"name": "IMG_FORMAT_10_10_10_2_SSCALED", "value": 47},
{"name": "IMG_FORMAT_10_10_10_2_UINT", "value": 48},
{"name": "IMG_FORMAT_10_10_10_2_SINT", "value": 49},
{"name": "IMG_FORMAT_2_10_10_10_UNORM", "value": 50},
{"name": "IMG_FORMAT_2_10_10_10_SNORM", "value": 51},
{"name": "IMG_FORMAT_2_10_10_10_USCALED", "value": 52},
{"name": "IMG_FORMAT_2_10_10_10_SSCALED", "value": 53},
{"name": "IMG_FORMAT_2_10_10_10_UINT", "value": 54},
{"name": "IMG_FORMAT_2_10_10_10_SINT", "value": 55},
{"name": "IMG_FORMAT_8_8_8_8_UNORM", "value": 56},
{"name": "IMG_FORMAT_8_8_8_8_SNORM", "value": 57},
{"name": "IMG_FORMAT_8_8_8_8_USCALED", "value": 58},
{"name": "IMG_FORMAT_8_8_8_8_SSCALED", "value": 59},
{"name": "IMG_FORMAT_8_8_8_8_UINT", "value": 60},
{"name": "IMG_FORMAT_8_8_8_8_SINT", "value": 61},
{"name": "IMG_FORMAT_32_32_UINT", "value": 62},
{"name": "IMG_FORMAT_32_32_SINT", "value": 63},
{"name": "IMG_FORMAT_32_32_FLOAT", "value": 64},
{"name": "IMG_FORMAT_16_16_16_16_UNORM", "value": 65},
{"name": "IMG_FORMAT_16_16_16_16_SNORM", "value": 66},
{"name": "IMG_FORMAT_16_16_16_16_USCALED", "value": 67},
{"name": "IMG_FORMAT_16_16_16_16_SSCALED", "value": 68},
{"name": "IMG_FORMAT_16_16_16_16_UINT", "value": 69},
{"name": "IMG_FORMAT_16_16_16_16_SINT", "value": 70},
{"name": "IMG_FORMAT_16_16_16_16_FLOAT", "value": 71},
{"flags": ["buffers_only"], "name": "IMG_FORMAT_32_32_32_UINT", "value": 72},
{"flags": ["buffers_only"], "name": "IMG_FORMAT_32_32_32_SINT", "value": 73},
{"flags": ["buffers_only"], "name": "IMG_FORMAT_32_32_32_FLOAT", "value": 74},
{"name": "IMG_FORMAT_32_32_32_32_UINT", "value": 75},
{"name": "IMG_FORMAT_32_32_32_32_SINT", "value": 76},
{"name": "IMG_FORMAT_32_32_32_32_FLOAT", "value": 77},
{"name": "IMG_FORMAT_8_SRGB", "value": 128},
{"name": "IMG_FORMAT_8_8_SRGB", "value": 129},
{"name": "IMG_FORMAT_8_8_8_8_SRGB", "value": 130},
{"name": "IMG_FORMAT_6E4_FLOAT", "value": 131},
{"name": "IMG_FORMAT_5_9_9_9_FLOAT", "value": 132},
{"name": "IMG_FORMAT_5_6_5_UNORM", "value": 133},
{"name": "IMG_FORMAT_1_5_5_5_UNORM", "value": 134},
{"name": "IMG_FORMAT_5_5_5_1_UNORM", "value": 135},
{"name": "IMG_FORMAT_4_4_4_4_UNORM", "value": 136},
{"name": "IMG_FORMAT_4_4_UNORM", "value": 137},
{"name": "IMG_FORMAT_1_UNORM", "value": 138},
{"name": "IMG_FORMAT_1_REVERSED_UNORM", "value": 139},
{"name": "IMG_FORMAT_32_FLOAT_CLAMP", "value": 140},
{"name": "IMG_FORMAT_8_24_UNORM", "value": 141},
{"name": "IMG_FORMAT_8_24_UINT", "value": 142},
{"name": "IMG_FORMAT_24_8_UNORM", "value": 143},
{"name": "IMG_FORMAT_24_8_UINT", "value": 144},
{"name": "IMG_FORMAT_X24_8_32_UINT", "value": 145},
{"name": "IMG_FORMAT_X24_8_32_FLOAT", "value": 146},
{"name": "IMG_FORMAT_GB_GR_UNORM", "value": 147},
{"name": "IMG_FORMAT_GB_GR_SNORM", "value": 148},
{"name": "IMG_FORMAT_GB_GR_UINT", "value": 149},
{"name": "IMG_FORMAT_GB_GR_SRGB", "value": 150},
{"name": "IMG_FORMAT_BG_RG_UNORM", "value": 151},
{"name": "IMG_FORMAT_BG_RG_SNORM", "value": 152},
{"name": "IMG_FORMAT_BG_RG_UINT", "value": 153},
{"name": "IMG_FORMAT_BG_RG_SRGB", "value": 154},
{"name": "IMG_FORMAT_FMASK8_S2_F1", "value": 156},
{"name": "IMG_FORMAT_FMASK8_S4_F1", "value": 157},
{"name": "IMG_FORMAT_FMASK8_S8_F1", "value": 158},
{"name": "IMG_FORMAT_FMASK8_S2_F2", "value": 159},
{"name": "IMG_FORMAT_FMASK8_S4_F2", "value": 160},
{"name": "IMG_FORMAT_FMASK8_S4_F4", "value": 161},
{"name": "IMG_FORMAT_FMASK16_S16_F1", "value": 162},
{"name": "IMG_FORMAT_FMASK16_S8_F2", "value": 163},
{"name": "IMG_FORMAT_FMASK32_S16_F2", "value": 164},
{"name": "IMG_FORMAT_FMASK32_S8_F4", "value": 165},
{"name": "IMG_FORMAT_FMASK32_S8_F8", "value": 166},
{"name": "IMG_FORMAT_FMASK64_S16_F4", "value": 167},
{"name": "IMG_FORMAT_FMASK64_S16_F8", "value": 168},
{"name": "IMG_FORMAT_BC1_UNORM", "value": 169},
{"name": "IMG_FORMAT_BC1_SRGB", "value": 170},
{"name": "IMG_FORMAT_BC2_UNORM", "value": 171},
{"name": "IMG_FORMAT_BC2_SRGB", "value": 172},
{"name": "IMG_FORMAT_BC3_UNORM", "value": 173},
{"name": "IMG_FORMAT_BC3_SRGB", "value": 174},
{"name": "IMG_FORMAT_BC4_UNORM", "value": 175},
{"name": "IMG_FORMAT_BC4_SNORM", "value": 176},
{"name": "IMG_FORMAT_BC5_UNORM", "value": 177},
{"name": "IMG_FORMAT_BC5_SNORM", "value": 178},
{"name": "IMG_FORMAT_BC6_UFLOAT", "value": 179},
{"name": "IMG_FORMAT_BC6_SFLOAT", "value": 180},
{"name": "IMG_FORMAT_BC7_UNORM", "value": 181},
{"name": "IMG_FORMAT_BC7_SRGB", "value": 182},
{"name": "IMG_FORMAT_MM_8_UNORM", "value": 265},
{"name": "IMG_FORMAT_MM_8_UINT", "value": 266},
{"name": "IMG_FORMAT_MM_8_8_UNORM", "value": 267},
{"name": "IMG_FORMAT_MM_8_8_UINT", "value": 268},
{"name": "IMG_FORMAT_MM_8_8_8_8_UNORM", "value": 269},
{"name": "IMG_FORMAT_MM_8_8_8_8_UINT", "value": 270},
{"name": "IMG_FORMAT_MM_VYUY8_UNORM", "value": 271},
{"name": "IMG_FORMAT_MM_VYUY8_UINT", "value": 272},
{"name": "IMG_FORMAT_MM_10_11_11_UNORM", "value": 273},
{"name": "IMG_FORMAT_MM_10_11_11_UINT", "value": 274},
{"name": "IMG_FORMAT_MM_2_10_10_10_UNORM", "value": 275},
{"name": "IMG_FORMAT_MM_2_10_10_10_UINT", "value": 276},
{"name": "IMG_FORMAT_MM_16_16_16_16_UNORM", "value": 277},
{"name": "IMG_FORMAT_MM_16_16_16_16_UINT", "value": 278},
{"name": "IMG_FORMAT_MM_10_IN_16_UNORM", "value": 279},
{"name": "IMG_FORMAT_MM_10_IN_16_UINT", "value": 280},
{"name": "IMG_FORMAT_MM_10_IN_16_16_UNORM", "value": 281},
{"name": "IMG_FORMAT_MM_10_IN_16_16_UINT", "value": 282},
{"name": "IMG_FORMAT_MM_10_IN_16_16_16_16_UNORM ", "value": 283},
{"name": "IMG_FORMAT_MM_10_IN_16_16_16_16_UINT", "value": 284},
{"name": "IMG_FORMAT_7E3_FLOAT", "value": 285},
{"name": "IMG_FORMAT_YCBCR_UNORM", "value": 286},
{"name": "IMG_FORMAT_YCBCR_SNORM", "value": 287},
{"name": "IMG_FORMAT_YCBCR_USCALED", "value": 288},
{"name": "IMG_FORMAT_YCBCR_SSCALED", "value": 289},
{"name": "IMG_FORMAT_YCBCR_UINT", "value": 290},
{"name": "IMG_FORMAT_YCBCR_SINT", "value": 291},
{"name": "IMG_FORMAT_YCBCR_SRGB", "value": 292}
]
},
"SQ_EXP_0__TGT": {
"entries": [
{"name": "SQ_EXP_MRT", "value": 0},
{"name": "SQ_EXP_MRTZ", "value": 8},
{"name": "SQ_EXP_NULL", "value": 9},
{"name": "SQ_EXP_POS", "value": 12},
{"name": "SQ_EXP_PRIM", "value": 20},
{"name": "SQ_EXP_PARAM", "value": 32}
]
},
"SQ_IMG_RSRC_WORD4__BC_SWIZZLE": {
"entries": [
{"name": "BC_SWIZZLE_XYZW", "value": 0},
{"name": "BC_SWIZZLE_XWYZ", "value": 1},
{"name": "BC_SWIZZLE_WZYX", "value": 2},
{"name": "BC_SWIZZLE_WXYZ", "value": 3},
{"name": "BC_SWIZZLE_ZYXW", "value": 4},
{"name": "BC_SWIZZLE_YXWZ", "value": 5}
]
}
},
"register_mappings": [
{
"chips": ["gfx10"],
"map": {"at": 36608, "to": "mm"},
"name": "SQ_BUF_RSRC_WORD0"
},
{
"chips": ["gfx10"],
"map": {"at": 36612, "to": "mm"},
"name": "SQ_BUF_RSRC_WORD1",
"type_ref": "SQ_BUF_RSRC_WORD1"
},
{
"chips": ["gfx10"],
"map": {"at": 36616, "to": "mm"},
"name": "SQ_BUF_RSRC_WORD2"
},
{
"chips": ["gfx10"],
"map": {"at": 36620, "to": "mm"},
"name": "SQ_BUF_RSRC_WORD3",
"type_ref": "SQ_BUF_RSRC_WORD3"
},
{
"chips": ["gfx10"],
"map": {"at": 36348, "to": "mm"},
"name": "SQ_EXP_0",
"type_ref": "SQ_EXP_0"
},
{
"chips": ["gfx10"],
"map": {"at": 40960, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD0"
},
{
"chips": ["gfx10"],
"map": {"at": 40964, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD1",
"type_ref": "SQ_IMG_RSRC_WORD1"
},
{
"chips": ["gfx10"],
"map": {"at": 40968, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD2",
"type_ref": "SQ_IMG_RSRC_WORD2"
},
{
"chips": ["gfx10"],
"map": {"at": 40972, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD3",
"type_ref": "SQ_IMG_RSRC_WORD3"
},
{
"chips": ["gfx10"],
"map": {"at": 40976, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD4",
"type_ref": "SQ_IMG_RSRC_WORD4"
},
{
"chips": ["gfx10"],
"map": {"at": 40980, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD5",
"type_ref": "SQ_IMG_RSRC_WORD5"
},
{
"chips": ["gfx10"],
"map": {"at": 40984, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD6",
"type_ref": "SQ_IMG_RSRC_WORD6"
},
{
"chips": ["gfx10"],
"map": {"at": 40988, "to": "mm"},
"name": "SQ_IMG_RSRC_WORD7"
},
{
"chips": ["gfx10"],
"map": {"at": 36656, "to": "mm"},
"name": "SQ_IMG_SAMP_WORD0",
"type_ref": "SQ_IMG_SAMP_WORD0"
},
{
"chips": ["gfx10"],
"map": {"at": 36660, "to": "mm"},
"name": "SQ_IMG_SAMP_WORD1",
"type_ref": "SQ_IMG_SAMP_WORD1"
},
{
"chips": ["gfx10"],
"map": {"at": 36664, "to": "mm"},
"name": "SQ_IMG_SAMP_WORD2",
"type_ref": "SQ_IMG_SAMP_WORD2"
},
{
"chips": ["gfx10"],
"map": {"at": 36668, "to": "mm"},
"name": "SQ_IMG_SAMP_WORD3",
"type_ref": "SQ_IMG_SAMP_WORD3"
}
],
"register_types": {
"SQ_BUF_RSRC_WORD1": {
"fields": [
{"bits": [0, 15], "name": "BASE_ADDRESS_HI"},
{"bits": [16, 29], "name": "STRIDE"},
{"bits": [30, 30], "name": "CACHE_SWIZZLE"},
{"bits": [31, 31], "name": "SWIZZLE_ENABLE"}
]
},
"SQ_BUF_RSRC_WORD3": {
"fields": [
{"bits": [0, 2], "name": "DST_SEL_X"},
{"bits": [3, 5], "name": "DST_SEL_Y"},
{"bits": [6, 8], "name": "DST_SEL_Z"},
{"bits": [9, 11], "name": "DST_SEL_W"},
{"bits": [12, 18], "enum_ref": "IMG_FORMAT", "name": "FORMAT"},
{"bits": [21, 22], "name": "INDEX_STRIDE"},
{"bits": [23, 23], "name": "ADD_TID_ENABLE"},
{"bits": [24, 24], "comment": "must be 1", "name": "RESOURCE_LEVEL"},
{"bits": [28, 29], "name": "OOB_SELECT"},
{"bits": [30, 31], "comment": "must be 0", "name": "TYPE"}
]
},
"SQ_EXP_0": {
"fields": [
{"bits": [0, 3], "name": "EN"},
{"bits": [4, 9], "enum_ref": "SQ_EXP_0__TGT", "name": "TGT"},
{"bits": [10, 10], "name": "COMPR"},
{"bits": [11, 11], "name": "DONE"},
{"bits": [12, 12], "name": "VM"}
]
},
"SQ_IMG_RSRC_WORD1": {
"fields": [
{"bits": [0, 7], "name": "BASE_ADDRESS_HI"},
{"bits": [8, 19], "name": "MIN_LOD"},
{"bits": [20, 28], "enum_ref": "IMG_FORMAT", "name": "FORMAT"},
{"bits": [30, 31], "name": "WIDTH_LO"}
]
},
"SQ_IMG_RSRC_WORD2": {
"fields": [
{"bits": [0, 13], "name": "WIDTH_HI"},
{"bits": [14, 29], "name": "HEIGHT"},
{"bits": [31, 31], "comment": "must be 1", "name": "RESOURCE_LEVEL"}
]
},
"SQ_IMG_RSRC_WORD3": {
"fields": [
{"bits": [0, 2], "name": "DST_SEL_X"},
{"bits": [3, 5], "name": "DST_SEL_Y"},
{"bits": [6, 8], "name": "DST_SEL_Z"},
{"bits": [9, 11], "name": "DST_SEL_W"},
{"bits": [12, 15], "name": "BASE_LEVEL"},
{"bits": [16, 19], "name": "LAST_LEVEL"},
{"bits": [20, 24], "name": "SW_MODE"},
{"bits": [25, 27], "enum_ref": "SQ_IMG_RSRC_WORD4__BC_SWIZZLE", "name": "BC_SWIZZLE"},
{"bits": [28, 31], "name": "TYPE"}
]
},
"SQ_IMG_RSRC_WORD4": {
"fields": [
{"bits": [0, 15], "name": "DEPTH"},
{"bits": [16, 31], "name": "BASE_ARRAY"}
]
},
"SQ_IMG_RSRC_WORD5": {
"fields": [
{"bits": [0, 3], "name": "ARRAY_PITCH"},
{"bits": [4, 7], "name": "MAX_MIP"},
{"bits": [8, 19], "name": "MIN_LOD_WARN"},
{"bits": [20, 22], "name": "PERF_MOD"},
{"bits": [23, 23], "name": "CORNER_SAMPLES"},
{"bits": [25, 25], "name": "LOD_HDW_CNT_EN"},
{"bits": [26, 26], "name": "PRT_DEFAULT"},
{"bits": [31, 31], "name": "BIG_PAGE"}
]
},
"SQ_IMG_RSRC_WORD6": {
"fields": [
{"bits": [0, 7], "name": "COUNTER_BANK_ID"},
{"bits": [10, 10], "name": "ITERATE_256"},
{"bits": [15, 16], "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
{"bits": [17, 18], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
{"bits": [19, 19], "name": "META_PIPE_ALIGNED"},
{"bits": [20, 20], "name": "WRITE_COMPRESS_ENABLE"},
{"bits": [21, 21], "name": "COMPRESSION_EN"},
{"bits": [22, 22], "name": "ALPHA_IS_ON_MSB"},
{"bits": [23, 23], "name": "COLOR_TRANSFORM"},
{"bits": [24, 31], "name": "META_DATA_ADDRESS_LO"}
]
},
"SQ_IMG_SAMP_WORD0": {
"fields": [
{"bits": [0, 2], "name": "CLAMP_X"},
{"bits": [3, 5], "name": "CLAMP_Y"},
{"bits": [6, 8], "name": "CLAMP_Z"},
{"bits": [9, 11], "name": "MAX_ANISO_RATIO"},
{"bits": [12, 14], "name": "DEPTH_COMPARE_FUNC"},
{"bits": [15, 15], "name": "FORCE_UNNORMALIZED"},
{"bits": [16, 18], "name": "ANISO_THRESHOLD"},
{"bits": [19, 19], "name": "MC_COORD_TRUNC"},
{"bits": [20, 20], "name": "FORCE_DEGAMMA"},
{"bits": [21, 26], "name": "ANISO_BIAS"},
{"bits": [27, 27], "name": "TRUNC_COORD"},
{"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"},
{"bits": [29, 30], "name": "FILTER_MODE"},
{"bits": [31, 31], "name": "SKIP_DEGAMMA"}
]
},
"SQ_IMG_SAMP_WORD1": {
"fields": [
{"bits": [0, 11], "name": "MIN_LOD"},
{"bits": [12, 23], "name": "MAX_LOD"},
{"bits": [24, 27], "name": "PERF_MIP"},
{"bits": [28, 31], "name": "PERF_Z"}
]
},
"SQ_IMG_SAMP_WORD2": {
"fields": [
{"bits": [0, 13], "name": "LOD_BIAS"},
{"bits": [0, 11], "comment": "if DERIV_ADJUST_EN == 1", "name": "BORDER_COLOR_PTR"},
{"bits": [12, 13], "comment": "if DERIV_ADJUST_EN == 1", "name": "BORDER_COLOR_TYPE"},
{"bits": [14, 19], "name": "LOD_BIAS_SEC"},
{"bits": [20, 21], "name": "XY_MAG_FILTER"},
{"bits": [22, 23], "name": "XY_MIN_FILTER"},
{"bits": [24, 25], "name": "Z_FILTER"},
{"bits": [26, 27], "name": "MIP_FILTER"},
{"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"},
{"bits": [29, 29], "name": "ANISO_OVERRIDE"},
{"bits": [30, 30], "name": "BLEND_ZERO_PRT"},
{"bits": [31, 31], "name": "DERIV_ADJUST_EN"}
]
},
"SQ_IMG_SAMP_WORD3": {
"fields": [
{"bits": [0, 11], "comment": "if DERIV_ADJUST_EN == 0", "name": "BORDER_COLOR_PTR"},
{"bits": [30, 31], "comment": "if DERIV_ADJUST_EN == 0", "name": "BORDER_COLOR_TYPE"}
]
}
}
}

21845
src/amd/registers/gfx10.json Normal file
View File

File diff suppressed because it is too large Load Diff

1
src/amd/registers/makeregheader.py
View File

@@ -49,6 +49,7 @@ CHIPS = [
Object(name='fiji', disambiguation='GFX8'),
Object(name='stoney', disambiguation='GFX8'),
Object(name='gfx9', disambiguation='GFX9'),
Object(name='gfx10', disambiguation='GFX10'),
]
######### END HARDCODED CONFIGURATION

109
src/amd/registers/pkt3.json
View File

@@ -88,6 +88,36 @@
{"name": "DATA", "value": 2},
{"name": "SRC_ADDR_TC_L2", "value": 3}
]
},
"GCR_GL1_RANGE": {
"entries": [
{"name": "GL1_ALL", "value": 0},
{"name": "GL1_RANGE", "value": 2},
{"name": "GL1_FIRST_LAST", "value": 3}
]
},
"GCR_GL2_RANGE": {
"entries": [
{"name": "GL2_ALL", "value": 0},
{"name": "GL2_VOL", "value": 1},
{"name": "GL2_RANGE", "value": 2},
{"name": "GL2_FIRST_LAST", "value": 3}
]
},
"GCR_GLI_INV": {
"entries": [
{"name": "GLI_NOP", "value": 0},
{"name": "GLI_ALL", "value": 1},
{"name": "GLI_RANGE", "value": 2},
{"name": "GLI_FIRST_LAST", "value": 3}
]
},
"GCR_SEQ": {
"entries": [
{"name": "SEQ_PARALLEL", "value": 0},
{"name": "SEQ_FORWARD", "value": 1},
{"name": "SEQ_REVERSE", "value": 2}
]
}
},
"register_mappings": [
@@ -98,7 +128,7 @@
"type_ref": "COMMAND"
},
{
"chips": ["gfx9"],
"chips": ["gfx9", "gfx10"],
"map": {"at": 1044, "to": "pkt3"},
"name": "COMMAND",
"type_ref": "COMMAND_gfx9"
@@ -110,13 +140,13 @@
"type_ref": "CONTROL"
},
{
"chips": ["gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 880, "to": "pkt3"},
"name": "CONTROL",
"type_ref": "CONTROL_cik"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 1040, "to": "pkt3"},
"name": "CP_DMA_WORD0",
"type_ref": "CP_DMA_WORD0"
@@ -134,19 +164,19 @@
"type_ref": "CP_DMA_WORD1_cik"
},
{
"chips": ["gfx9"],
"chips": ["gfx9", "gfx10"],
"map": {"at": 1041, "to": "pkt3"},
"name": "CP_DMA_WORD1",
"type_ref": "CP_DMA_WORD1_gfx9"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 1042, "to": "pkt3"},
"name": "CP_DMA_WORD2",
"type_ref": "CP_DMA_WORD2"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 1043, "to": "pkt3"},
"name": "CP_DMA_WORD3",
"type_ref": "CP_DMA_WORD3"
@@ -164,54 +194,66 @@
"type_ref": "DMA_DATA_WORD0_cik"
},
{
"chips": ["gfx9"],
"chips": ["gfx9", "gfx10"],
"map": {"at": 1280, "to": "pkt3"},
"name": "DMA_DATA_WORD0",
"type_ref": "DMA_DATA_WORD0_gfx9"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 882, "to": "pkt3"},
"name": "DST_ADDR_HI"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 1284, "to": "pkt3"},
"name": "DST_ADDR_HI"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 881, "to": "pkt3"},
"name": "DST_ADDR_LO"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 1283, "to": "pkt3"},
"name": "DST_ADDR_LO"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx10"],
"map": {"at": 1414, "to": "pkt3"},
"name": "GCR_CNTL",
"type_ref": "GCR_CNTL"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 1009, "to": "pkt3"},
"name": "IB_BASE_HI"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 1008, "to": "pkt3"},
"name": "IB_BASE_LO"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 1010, "to": "pkt3"},
"name": "IB_CONTROL",
"type_ref": "IB_CONTROL"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx10"],
"map": {"at": 1168, "to": "pkt3"},
"name": "RELEASE_MEM_OP",
"type_ref": "RELEASE_MEM_OP"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 1282, "to": "pkt3"},
"name": "SRC_ADDR_HI"
},
{
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
"chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9", "gfx10"],
"map": {"at": 1281, "to": "pkt3"},
"name": "SRC_ADDR_LO"
}
@@ -327,12 +369,47 @@
{"bits": [31, 31], "name": "CP_SYNC"}
]
},
"GCR_CNTL": {
"fields": [
{"bits": [0, 1], "enum_ref": "GCR_GLI_INV", "name": "GLI_INV"},
{"bits": [2, 3], "enum_ref": "GCR_GL1_RANGE", "name": "GL1_RANGE"},
{"bits": [4, 4], "name": "GLM_WB"},
{"bits": [5, 5], "name": "GLM_INV"},
{"bits": [6, 6], "name": "GLK_WB"},
{"bits": [7, 7], "name": "GLK_INV"},
{"bits": [8, 8], "name": "GLV_INV"},
{"bits": [9, 9], "name": "GL1_INV"},
{"bits": [10, 10], "name": "GL2_US"},
{"bits": [11, 12], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
{"bits": [13, 13], "name": "GL2_DISCARD"},
{"bits": [14, 14], "name": "GL2_INV"},
{"bits": [15, 15], "name": "GL2_WB"},
{"bits": [16, 17], "enum_ref": "GCR_SEQ", "name": "SEQ"},
{"bits": [18, 18], "name": "RANGE_IS_PA"}
]
},
"IB_CONTROL": {
"fields": [
{"bits": [0, 19], "name": "IB_SIZE"},
{"bits": [20, 20], "name": "CHAIN"},
{"bits": [23, 23], "name": "VALID"}
]
},
"RELEASE_MEM_OP": {
"fields": [
{"bits": [0, 5], "name": "EVENT_TYPE"},
{"bits": [8, 11], "name": "EVENT_INDEX"},
{"bits": [12, 12], "name": "GLM_WB"},
{"bits": [13, 13], "name": "GLM_INV"},
{"bits": [14, 14], "name": "GLV_INV"},
{"bits": [15, 15], "name": "GL1_INV"},
{"bits": [16, 16], "name": "GL2_US"},
{"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"},
{"bits": [19, 19], "name": "GL2_DISCARD"},
{"bits": [20, 20], "name": "GL2_INV"},
{"bits": [21, 21], "name": "GL2_WB"},
{"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"}
]
}
}
}

6
src/amd/vulkan/radv_device.c
View File

@@ -4356,7 +4356,7 @@ radv_initialise_color_surface(struct radv_device *device,
uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
S_028C6C_SLICE_MAX(max_slice);
S_028C6C_SLICE_MAX_GFX6(max_slice);
if (iview->image->info.samples > 1) {
unsigned log_samples = util_logbase2(iview->image->info.samples);
@@ -4461,7 +4461,7 @@ radv_initialise_color_surface(struct radv_device *device,
unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
@@ -4908,7 +4908,7 @@ radv_init_sampler(struct radv_device *device,
S_008F38_MIP_POINT_PRECLAMP(0) |
S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
S_008F38_FILTER_PREC_FIX(1) |
S_008F38_ANISO_OVERRIDE(is_vi));
S_008F38_ANISO_OVERRIDE_GFX6(is_vi));
sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
}

2
src/amd/vulkan/radv_pipeline.c
View File

@@ -3094,7 +3094,7 @@ radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
radeon_emit(cs, shader->rsrc1);
radeon_emit(cs, shader->rsrc2 |
S_00B42C_LDS_SIZE(tess->lds_size));
S_00B42C_LDS_SIZE_GFX9(tess->lds_size));
} else {
radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
radeon_emit(cs, va >> 8);

2
src/amd/vulkan/radv_shader.c
View File

@@ -482,7 +482,7 @@ radv_fill_shader_variant(struct radv_device *device,
variant->code_size = radv_get_shader_binary_size(binary);
variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) |
S_00B12C_USER_SGPR_MSB_GFX9(variant->info.num_user_sgprs >> 5) |
S_00B12C_SCRATCH_EN(scratch_enabled) |
S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |

6
src/gallium/drivers/radeonsi/si_state.c
View File

@@ -2526,12 +2526,12 @@ static void si_initialize_color_surface(struct si_context *sctx,
}
unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
S_028C6C_SLICE_MAX_GFX6(surf->base.u.tex.last_layer);
if (sctx->chip_class >= GFX9) {
unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
@@ -4371,7 +4371,7 @@ static void *si_create_sampler_state(struct pipe_context *ctx,
S_008F38_MIP_POINT_PRECLAMP(0) |
S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
S_008F38_FILTER_PREC_FIX(1) |
S_008F38_ANISO_OVERRIDE(sctx->chip_class >= GFX8));
S_008F38_ANISO_OVERRIDE_GFX6(sctx->chip_class >= GFX8));
rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
/* Create sampler resource for integer textures. */

2
src/gallium/drivers/radeonsi/si_state_draw.c
View File

@@ -259,7 +259,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
if (sctx->chip_class >= GFX9) {
unsigned hs_rsrc2 = ls_current->config.rsrc2 |
S_00B42C_LDS_SIZE(lds_size);
S_00B42C_LDS_SIZE_GFX9(lds_size);
radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);

4
src/gallium/drivers/radeonsi/si_state_shaders.c
View File

@@ -522,7 +522,7 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
shader->config.rsrc2 =
S_00B42C_USER_SGPR(num_user_sgprs) |
S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5) |
S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
} else {
si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
@@ -906,7 +906,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
S_00B22C_USER_SGPR(num_user_sgprs) |
S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5) |
S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
S_00B22C_LDS_SIZE(shader->config.lds_size) |