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glsl,nir: Move i/umulExtended lowering to NIR.

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NIR already has the necessary lowering, and the GLSL lowering violates
GLSL IR validation rules.  Once quadop lowering was turned off, the IR
validation at the end of the compile path on DEBUG builds caught the
problem.

In order to move the lowering to NIR, though, we need to make sure that
drivers supporting these functions actually have the lowering flag set.

xfails added for t860, where apparently this tickles a variety of existing
64-bit bugs in the backend.

Fixes: #6461
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16437>
This commit is contained in:
Emma Anholt
2022-05-10 10:31:07 -07:00
committed by Marge Bot
parent 6f0db3778f
commit 7472bb4bad
12 changed files with 15 additions and 73 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/compiler/glsl/ir_optimization.h
View File

@@ -55,7 +55,6 @@ struct gl_shader_program;
#define DDIV_TO_MUL_RCP 0x100000
#define DIV_TO_MUL_RCP (FDIV_TO_MUL_RCP | DDIV_TO_MUL_RCP)
#define SQRT_TO_ABS_SQRT 0x200000
#define MUL64_TO_MUL_AND_MUL_HIGH 0x400000
/* Operations for lower_64bit_integer_instructions() */
#define DIV64 (1U << 0)

70
src/compiler/glsl/lower_instructions.cpp
View File

@@ -157,7 +157,6 @@ private:
void find_msb_to_float_cast(ir_expression *ir);
void imul_high_to_mul(ir_expression *ir);
void sqrt_to_abs_sqrt(ir_expression *ir);
void mul64_to_mul_and_mul_high(ir_expression *ir);
ir_expression *_carry(operand a, operand b);
@@ -1615,66 +1614,6 @@ lower_instructions_visitor::sqrt_to_abs_sqrt(ir_expression *ir)
this->progress = true;
}
void
lower_instructions_visitor::mul64_to_mul_and_mul_high(ir_expression *ir)
{
/* Lower 32x32-> 64 to
* msb = imul_high(x_lo, y_lo)
* lsb = mul(x_lo, y_lo)
*/
const unsigned elements = ir->operands[0]->type->vector_elements;
const ir_expression_operation operation =
ir->type->base_type == GLSL_TYPE_UINT64 ? ir_unop_pack_uint_2x32
: ir_unop_pack_int_2x32;
const glsl_type *var_type = ir->type->base_type == GLSL_TYPE_UINT64
? glsl_type::uvec(elements)
: glsl_type::ivec(elements);
const glsl_type *ret_type = ir->type->base_type == GLSL_TYPE_UINT64
? glsl_type::uvec2_type
: glsl_type::ivec2_type;
ir_instruction &i = *base_ir;
ir_variable *msb =
new(ir) ir_variable(var_type, "msb", ir_var_temporary);
ir_variable *lsb =
new(ir) ir_variable(var_type, "lsb", ir_var_temporary);
ir_variable *x =
new(ir) ir_variable(var_type, "x", ir_var_temporary);
ir_variable *y =
new(ir) ir_variable(var_type, "y", ir_var_temporary);
i.insert_before(x);
i.insert_before(assign(x, ir->operands[0]));
i.insert_before(y);
i.insert_before(assign(y, ir->operands[1]));
i.insert_before(msb);
i.insert_before(lsb);
i.insert_before(assign(msb, imul_high(x, y)));
i.insert_before(assign(lsb, mul(x, y)));
ir_rvalue *result[4] = {NULL};
for (unsigned elem = 0; elem < elements; elem++) {
ir_rvalue *val = new(ir) ir_expression(ir_quadop_vector, ret_type,
swizzle(lsb, elem, 1),
swizzle(msb, elem, 1), NULL, NULL);
result[elem] = expr(operation, val);
}
ir->operation = ir_quadop_vector;
ir->init_num_operands();
ir->operands[0] = result[0];
ir->operands[1] = result[1];
ir->operands[2] = result[2];
ir->operands[3] = result[3];
this->progress = true;
}
ir_visitor_status
lower_instructions_visitor::visit_leave(ir_expression *ir)
{
@@ -1802,15 +1741,6 @@ lower_instructions_visitor::visit_leave(ir_expression *ir)
imul_high_to_mul(ir);
break;
case ir_binop_mul:
if (lowering(MUL64_TO_MUL_AND_MUL_HIGH) &&
(ir->type->base_type == GLSL_TYPE_INT64 ||
ir->type->base_type == GLSL_TYPE_UINT64) &&
(ir->operands[0]->type->base_type == GLSL_TYPE_INT ||
ir->operands[1]->type->base_type == GLSL_TYPE_UINT))
mul64_to_mul_and_mul_high(ir);
break;
case ir_unop_rsq:
case ir_unop_sqrt:
if (lowering(SQRT_TO_ABS_SQRT))