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freedreno/registers: Add a couple things used on kernel side

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Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6900>
This commit is contained in:
Rob Clark
2020-09-28 15:00:11 -07:00
committed by Marge Bot
parent 27c8d97657
commit 7454ae4ea6
3 changed files with 6 additions and 2 deletions
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2
src/freedreno/.gitlab-ci/reference/afuc_test.asm
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@@ -207,7 +207,7 @@ CP_CONTEXT_UPDATE:
CP_SET_PROTECTED_MODE:
UNKN96:
UNKN97:
UNKN98:
CP_WHERE_AM_I:
CP_SET_MODE:
CP_SET_VISIBILITY_OVERRIDE:
CP_SET_MARKER:

5
src/freedreno/registers/adreno/a5xx.xml
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@@ -1538,7 +1538,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<reg32 offset="0x0e55" name="VFD_PERFCTR_VFD_SEL_5" type="a5xx_vfd_perfcounter_select"/>
<reg32 offset="0x0e56" name="VFD_PERFCTR_VFD_SEL_6" type="a5xx_vfd_perfcounter_select"/>
<reg32 offset="0x0e57" name="VFD_PERFCTR_VFD_SEL_7" type="a5xx_vfd_perfcounter_select"/>
<reg32 offset="0x0e60" name="VPC_DBG_ECO_CNTL"/> <!-- always 00000400? -->
<reg32 offset="0x0e60" name="VPC_DBG_ECO_CNTL">
<bitfield name="ALLFLATOPTDIS" pos="10" type="boolean"/>
</reg32>
<reg32 offset="0x0e61" name="VPC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<reg32 offset="0x0e62" name="VPC_MODE_CNTL">
<bitfield name="BINNING_PASS" pos="0" type="boolean"/>
@@ -1549,6 +1551,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_3" type="a5xx_vpc_perfcounter_select"/>
<reg32 offset="0x0e80" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<reg32 offset="0x0e81" name="UCHE_MODE_CNTL"/>
<reg32 offset="0x0e82" name="UCHE_SVM_CNTL"/>
<reg32 offset="0x0e87" name="UCHE_WRITE_THRU_BASE_LO"/>
<reg32 offset="0x0e88" name="UCHE_WRITE_THRU_BASE_HI"/>

1
src/freedreno/registers/adreno/adreno_pm4.xml
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@@ -383,6 +383,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" varset="chip" variants="A5XX-"/>
<value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" varset="chip" variants="A5XX-"/>
<value name="CP_SET_SUBDRAW_SIZE" value="0x35" varset="chip" variants="A5XX-"/>
<value name="CP_WHERE_AM_I" value="0x62" varset="chip" variants="A5XX-"/>
<value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" varset="chip" variants="A5XX-"/>
<!-- Enable/Disable/Defer A5x global preemption model -->
<value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" varset="chip" variants="A5XX"/>