r600/sfn: lower VS output IO
Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7715>
This commit is contained in:
@@ -825,8 +825,13 @@ int r600_shader_from_nir(struct r600_context *rctx,
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NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, r600_glsl_type_size,
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nir_lower_io_lower_64bit_to_32);
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if (sel->nir->info.stage == MESA_SHADER_VERTEX)
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if (sel->nir->info.stage == MESA_SHADER_VERTEX) {
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NIR_PASS_V(sel->nir, r600_vectorize_vs_inputs);
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NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size,
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nir_lower_io_lower_64bit_to_32);
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if (key->vs.as_ls)
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NIR_PASS_V(sel->nir, r600_lower_tess_io, (pipe_prim_type)key->tcs.prim_mode);
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}
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if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
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NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, r600_glsl_type_size,
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@@ -836,8 +841,7 @@ int r600_shader_from_nir(struct r600_context *rctx,
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NIR_PASS_V(sel->nir, r600_lower_fs_out_to_vector);
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}
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if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL ||
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(sel->nir->info.stage == MESA_SHADER_VERTEX && key->vs.as_ls)) {
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if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL) {
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NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size,
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nir_lower_io_lower_64bit_to_32);
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NIR_PASS_V(sel->nir, r600_lower_tess_io, (pipe_prim_type)key->tcs.prim_mode);
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@@ -850,8 +854,7 @@ int r600_shader_from_nir(struct r600_context *rctx,
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}
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if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL ||
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sel->nir->info.stage == MESA_SHADER_TESS_EVAL ||
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(sel->nir->info.stage == MESA_SHADER_VERTEX && key->vs.as_ls)) {
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sel->nir->info.stage == MESA_SHADER_TESS_EVAL) {
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auto prim_type = sel->nir->info.stage == MESA_SHADER_TESS_CTRL ?
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key->tcs.prim_mode : sel->nir->info.tess.primitive_mode;
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NIR_PASS_V(sel->nir, r600_lower_tess_io, static_cast<pipe_prim_type>(prim_type));
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@@ -1,6 +1,6 @@
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#include "sfn_nir.h"
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bool r600_lower_tess_io_filter(const nir_instr *instr)
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bool r600_lower_tess_io_filter(const nir_instr *instr, gl_shader_stage stage)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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@@ -8,7 +8,6 @@ bool r600_lower_tess_io_filter(const nir_instr *instr)
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nir_intrinsic_instr *op = nir_instr_as_intrinsic(instr);
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switch (op->intrinsic) {
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case nir_intrinsic_load_input:
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case nir_intrinsic_store_output:
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case nir_intrinsic_load_output:
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case nir_intrinsic_load_per_vertex_input:
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case nir_intrinsic_load_per_vertex_output:
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@@ -17,6 +16,8 @@ bool r600_lower_tess_io_filter(const nir_instr *instr)
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case nir_intrinsic_load_tess_level_outer:
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case nir_intrinsic_load_tess_level_inner:
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return true;
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case nir_intrinsic_store_output:
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return stage == MESA_SHADER_TESS_CTRL || stage == MESA_SHADER_VERTEX;
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default:
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;
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}
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@@ -326,7 +327,7 @@ bool r600_lower_tess_io(nir_shader *shader, enum pipe_prim_type prim_type)
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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if (r600_lower_tess_io_filter(instr))
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if (r600_lower_tess_io_filter(instr, shader->info.stage))
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progress |= r600_lower_tess_io_impl(&b, instr, prim_type);
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}
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}
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@@ -134,6 +134,7 @@ bool VertexShaderFromNir::do_allocate_reserved_registers()
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void VertexShaderFromNir::emit_shader_start()
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{
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m_export_processor->emit_shader_start();
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}
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bool VertexShaderFromNir::scan_sysvalue_access(nir_instr *instr)
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@@ -151,6 +152,8 @@ bool VertexShaderFromNir::scan_sysvalue_access(nir_instr *instr)
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case nir_intrinsic_load_tcs_rel_patch_id_r600:
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m_sv_values.set(es_rel_patch_id);
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break;
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case nir_intrinsic_store_output:
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m_export_processor->scan_store_output(ii);
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default:
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;
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}
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@@ -172,6 +175,8 @@ bool VertexShaderFromNir::emit_intrinsic_instruction_override(nir_intrinsic_inst
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return load_preloaded_value(instr->dest, 0, m_instance_id);
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case nir_intrinsic_store_local_shared_r600:
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return emit_store_local_shared(instr);
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case nir_intrinsic_store_output:
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return m_export_processor->store_output(instr);
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default:
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return false;
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}
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