From 7421f9d95bd67d29880de18b6a09a87dc2af6658 Mon Sep 17 00:00:00 2001 From: Gert Wollny Date: Mon, 23 Nov 2020 11:45:59 +0100 Subject: [PATCH] r600/sfn: lower VS output IO Signed-off-by: Gert Wollny Part-of: --- src/gallium/drivers/r600/sfn/sfn_nir.cpp | 13 ++++++++----- .../drivers/r600/sfn/sfn_nir_lower_tess_io.cpp | 7 ++++--- src/gallium/drivers/r600/sfn/sfn_shader_vertex.cpp | 5 +++++ 3 files changed, 17 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/r600/sfn/sfn_nir.cpp b/src/gallium/drivers/r600/sfn/sfn_nir.cpp index 89cc7b10987..4e8fd2bcab6 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir.cpp @@ -825,8 +825,13 @@ int r600_shader_from_nir(struct r600_context *rctx, NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, r600_glsl_type_size, nir_lower_io_lower_64bit_to_32); - if (sel->nir->info.stage == MESA_SHADER_VERTEX) + if (sel->nir->info.stage == MESA_SHADER_VERTEX) { NIR_PASS_V(sel->nir, r600_vectorize_vs_inputs); + NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size, + nir_lower_io_lower_64bit_to_32); + if (key->vs.as_ls) + NIR_PASS_V(sel->nir, r600_lower_tess_io, (pipe_prim_type)key->tcs.prim_mode); + } if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) { NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, r600_glsl_type_size, @@ -836,8 +841,7 @@ int r600_shader_from_nir(struct r600_context *rctx, NIR_PASS_V(sel->nir, r600_lower_fs_out_to_vector); } - if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL || - (sel->nir->info.stage == MESA_SHADER_VERTEX && key->vs.as_ls)) { + if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL) { NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size, nir_lower_io_lower_64bit_to_32); NIR_PASS_V(sel->nir, r600_lower_tess_io, (pipe_prim_type)key->tcs.prim_mode); @@ -850,8 +854,7 @@ int r600_shader_from_nir(struct r600_context *rctx, } if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL || - sel->nir->info.stage == MESA_SHADER_TESS_EVAL || - (sel->nir->info.stage == MESA_SHADER_VERTEX && key->vs.as_ls)) { + sel->nir->info.stage == MESA_SHADER_TESS_EVAL) { auto prim_type = sel->nir->info.stage == MESA_SHADER_TESS_CTRL ? key->tcs.prim_mode : sel->nir->info.tess.primitive_mode; NIR_PASS_V(sel->nir, r600_lower_tess_io, static_cast(prim_type)); diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp b/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp index 7781361cd86..21015e0434d 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp @@ -1,6 +1,6 @@ #include "sfn_nir.h" -bool r600_lower_tess_io_filter(const nir_instr *instr) +bool r600_lower_tess_io_filter(const nir_instr *instr, gl_shader_stage stage) { if (instr->type != nir_instr_type_intrinsic) return false; @@ -8,7 +8,6 @@ bool r600_lower_tess_io_filter(const nir_instr *instr) nir_intrinsic_instr *op = nir_instr_as_intrinsic(instr); switch (op->intrinsic) { case nir_intrinsic_load_input: - case nir_intrinsic_store_output: case nir_intrinsic_load_output: case nir_intrinsic_load_per_vertex_input: case nir_intrinsic_load_per_vertex_output: @@ -17,6 +16,8 @@ bool r600_lower_tess_io_filter(const nir_instr *instr) case nir_intrinsic_load_tess_level_outer: case nir_intrinsic_load_tess_level_inner: return true; + case nir_intrinsic_store_output: + return stage == MESA_SHADER_TESS_CTRL || stage == MESA_SHADER_VERTEX; default: ; } @@ -326,7 +327,7 @@ bool r600_lower_tess_io(nir_shader *shader, enum pipe_prim_type prim_type) if (instr->type != nir_instr_type_intrinsic) continue; - if (r600_lower_tess_io_filter(instr)) + if (r600_lower_tess_io_filter(instr, shader->info.stage)) progress |= r600_lower_tess_io_impl(&b, instr, prim_type); } } diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_vertex.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_vertex.cpp index 86c4c38e2ac..c52be4412f4 100644 --- a/src/gallium/drivers/r600/sfn/sfn_shader_vertex.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_shader_vertex.cpp @@ -134,6 +134,7 @@ bool VertexShaderFromNir::do_allocate_reserved_registers() void VertexShaderFromNir::emit_shader_start() { + m_export_processor->emit_shader_start(); } bool VertexShaderFromNir::scan_sysvalue_access(nir_instr *instr) @@ -151,6 +152,8 @@ bool VertexShaderFromNir::scan_sysvalue_access(nir_instr *instr) case nir_intrinsic_load_tcs_rel_patch_id_r600: m_sv_values.set(es_rel_patch_id); break; + case nir_intrinsic_store_output: + m_export_processor->scan_store_output(ii); default: ; } @@ -172,6 +175,8 @@ bool VertexShaderFromNir::emit_intrinsic_instruction_override(nir_intrinsic_inst return load_preloaded_value(instr->dest, 0, m_instance_id); case nir_intrinsic_store_local_shared_r600: return emit_store_local_shared(instr); + case nir_intrinsic_store_output: + return m_export_processor->store_output(instr); default: return false; }