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radeonsi: generate image load/store/atomic ops using ac_build_image_opcode

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In preparation of dimension-aware LLVM image intrinsics.

Acked-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle
2018-04-20 09:29:57 +02:00
parent 625dcbbc45
commit 74063431f1
4 changed files with 209 additions and 163 deletions
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37
src/amd/common/ac_llvm_build.h
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@@ -313,8 +313,25 @@ enum ac_image_opcode {
ac_image_gather4,
ac_image_load,
ac_image_load_mip,
ac_image_store,
ac_image_store_mip,
ac_image_get_lod,
ac_image_get_resinfo,
ac_image_atomic,
ac_image_atomic_cmpswap,
};
enum ac_atomic_op {
ac_atomic_swap,
ac_atomic_add,
ac_atomic_sub,
ac_atomic_smin,
ac_atomic_umin,
ac_atomic_smax,
ac_atomic_umax,
ac_atomic_and,
ac_atomic_or,
ac_atomic_xor,
};
enum ac_image_dim {
@@ -328,21 +345,31 @@ enum ac_image_dim {
ac_image_2darraymsaa,
};
/* These cache policy bits match the definitions used by the LLVM intrinsics. */
enum ac_image_cache_policy {
ac_glc = 1 << 0,
ac_slc = 1 << 1,
};
struct ac_image_args {
enum ac_image_opcode opcode;
enum ac_image_dim dim;
enum ac_image_opcode opcode : 4;
enum ac_atomic_op atomic : 4; /* for the ac_image_atomic opcode */
enum ac_image_dim dim : 3;
unsigned dmask : 4;
unsigned cache_policy : 2;
bool unorm : 1;
bool level_zero : 1;
unsigned attributes; /* additional call-site specific AC_FUNC_ATTRs */
LLVMValueRef resource;
LLVMValueRef sampler;
LLVMValueRef data[2]; /* data[0] is source data (vector); data[1] is cmp for cmpswap */
LLVMValueRef offset;
LLVMValueRef bias;
LLVMValueRef compare;
LLVMValueRef derivs[6];
LLVMValueRef coords[4];
LLVMValueRef lod; // also used by ac_image_get_resinfo
unsigned dmask;
bool unorm;
bool level_zero;
};
LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,