intel/compiler: validate region restrictions for half-float conversions
v2: - Consider implicit conversions in 2-src instructions too (Curro) - For restrictions that involve destination stride requirements only validate them for Align1, since Align16 always requires packed data. - Skip general rule for the dst/execution type size ratio for mixed float instructions on CHV and SKL+, these have their own set of rules that we'll be validated separately. v3 (Curro): - Do not check src1 type in single-source instructions. - Check restriction on src1. - Remove invalid test. Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Iago Toral Quiroga
committed by
Juan A. Suarez Romero
Juan A. Suarez Romero
parent
6ff52f0628
commit
7376d57a9c
@@ -469,6 +469,66 @@ is_packed(unsigned vstride, unsigned width, unsigned hstride)
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return false;
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return false;
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}
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}
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/**
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* Returns whether an instruction is an explicit or implicit conversion
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* to/from half-float.
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*/
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static bool
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is_half_float_conversion(const struct gen_device_info *devinfo,
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const brw_inst *inst)
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{
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enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
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unsigned num_sources = num_sources_from_inst(devinfo, inst);
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enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
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if (dst_type != src0_type &&
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(dst_type == BRW_REGISTER_TYPE_HF || src0_type == BRW_REGISTER_TYPE_HF)) {
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return true;
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} else if (num_sources > 1) {
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enum brw_reg_type src1_type = brw_inst_src1_type(devinfo, inst);
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return dst_type != src1_type &&
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(dst_type == BRW_REGISTER_TYPE_HF ||
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src1_type == BRW_REGISTER_TYPE_HF);
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}
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return false;
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}
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/*
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* Returns whether an instruction is using mixed float operation mode
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*/
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static bool
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is_mixed_float(const struct gen_device_info *devinfo, const brw_inst *inst)
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{
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if (devinfo->gen < 8)
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return false;
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if (inst_is_send(devinfo, inst))
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return false;
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unsigned opcode = brw_inst_opcode(devinfo, inst);
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const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
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if (desc->ndst == 0)
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return false;
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/* FIXME: support 3-src instructions */
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unsigned num_sources = num_sources_from_inst(devinfo, inst);
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assert(num_sources < 3);
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enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
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enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
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if (num_sources == 1)
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return types_are_mixed_float(src0_type, dst_type);
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enum brw_reg_type src1_type = brw_inst_src1_type(devinfo, inst);
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return types_are_mixed_float(src0_type, src1_type) ||
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types_are_mixed_float(src0_type, dst_type) ||
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types_are_mixed_float(src1_type, dst_type);
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}
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/**
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/**
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* Checks restrictions listed in "General Restrictions Based on Operand Types"
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* Checks restrictions listed in "General Restrictions Based on Operand Types"
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* in the "Register Region Restrictions" section.
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* in the "Register Region Restrictions" section.
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@@ -539,7 +599,100 @@ general_restrictions_based_on_operand_types(const struct gen_device_info *devinf
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exec_type_size == 8 && dst_type_size == 4)
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exec_type_size == 8 && dst_type_size == 4)
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dst_type_size = 8;
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dst_type_size = 8;
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if (exec_type_size > dst_type_size) {
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if (is_half_float_conversion(devinfo, inst)) {
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/**
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* A helper to validate used in the validation of the following restriction
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* from the BDW+ PRM, Volume 2a, Command Reference, Instructions - MOV:
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*
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* "There is no direct conversion from HF to DF or DF to HF.
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* There is no direct conversion from HF to Q/UQ or Q/UQ to HF."
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*
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* Even if these restrictions are listed for the MOV instruction, we
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* validate this more generally, since there is the possibility
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* of implicit conversions from other instructions, such us implicit
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* conversion from integer to HF with the ADD instruction in SKL+.
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*/
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enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
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enum brw_reg_type src1_type = num_sources > 1 ?
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brw_inst_src1_type(devinfo, inst) : 0;
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ERROR_IF(dst_type == BRW_REGISTER_TYPE_HF &&
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(type_sz(src0_type) == 8 ||
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(num_sources > 1 && type_sz(src1_type) == 8)),
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"There are no direct conversions between 64-bit types and HF");
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ERROR_IF(type_sz(dst_type) == 8 &&
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(src0_type == BRW_REGISTER_TYPE_HF ||
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(num_sources > 1 && src1_type == BRW_REGISTER_TYPE_HF)),
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"There are no direct conversions between 64-bit types and HF");
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/* From the BDW+ PRM:
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*
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* "Conversion between Integer and HF (Half Float) must be
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* DWord-aligned and strided by a DWord on the destination."
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*
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* Also, the above restrictions seems to be expanded on CHV and SKL+ by:
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*
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* "There is a relaxed alignment rule for word destinations. When
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* the destination type is word (UW, W, HF), destination data types
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* can be aligned to either the lowest word or the second lowest
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* word of the execution channel. This means the destination data
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* words can be either all in the even word locations or all in the
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* odd word locations."
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*
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* We do not implement the second rule as is though, since empirical
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* testing shows inconsistencies:
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* - It suggests that packed 16-bit is not allowed, which is not true.
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* - It suggests that conversions from Q/DF to W (which need to be
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* 64-bit aligned on the destination) are not possible, which is
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* not true.
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*
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* So from this rule we only validate the implication that conversions
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* from F to HF need to be DWord strided (except in Align1 mixed
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* float mode where packed fp16 destination is allowed so long as the
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* destination is oword-aligned).
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*
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* Finally, we only validate this for Align1 because Align16 always
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* requires packed destinations, so these restrictions can't possibly
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* apply to Align16 mode.
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*/
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
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if ((dst_type == BRW_REGISTER_TYPE_HF &&
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(brw_reg_type_is_integer(src0_type) ||
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(num_sources > 1 && brw_reg_type_is_integer(src1_type)))) ||
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(brw_reg_type_is_integer(dst_type) &&
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(src0_type == BRW_REGISTER_TYPE_HF ||
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(num_sources > 1 && src1_type == BRW_REGISTER_TYPE_HF)))) {
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ERROR_IF(dst_stride * dst_type_size != 4,
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"Conversions between integer and half-float must be "
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"strided by a DWord on the destination");
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unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
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ERROR_IF(subreg % 4 != 0,
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"Conversions between integer and half-float must be "
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"aligned to a DWord on the destination");
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} else if ((devinfo->is_cherryview || devinfo->gen >= 9) &&
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dst_type == BRW_REGISTER_TYPE_HF) {
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unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
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ERROR_IF(dst_stride != 2 &&
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!(is_mixed_float(devinfo, inst) &&
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dst_stride == 1 && subreg % 16 == 0),
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"Conversions to HF must have either all words in even "
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"word locations or all words in odd word locations or "
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"be mixed-float with Oword-aligned packed destination");
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}
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}
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}
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/* There are special regioning rules for mixed-float mode in CHV and SKL that
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* override the general rule for the ratio of sizes of the destination type
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* and the execution type. We will add validation for those in a later patch.
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*/
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bool validate_dst_size_and_exec_size_ratio =
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!is_mixed_float(devinfo, inst) ||
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!(devinfo->is_cherryview || devinfo->gen >= 9);
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if (validate_dst_size_and_exec_size_ratio &&
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exec_type_size > dst_type_size) {
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if (!(dst_type_is_byte && inst_is_raw_move(devinfo, inst))) {
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if (!(dst_type_is_byte && inst_is_raw_move(devinfo, inst))) {
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ERROR_IF(dst_stride * dst_type_size != exec_type_size,
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ERROR_IF(dst_stride * dst_type_size != exec_type_size,
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"Destination stride must be equal to the ratio of the sizes "
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"Destination stride must be equal to the ratio of the sizes "
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@@ -848,6 +848,122 @@ TEST_P(validation_test, byte_destination_relaxed_alignment)
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}
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}
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}
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}
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TEST_P(validation_test, half_float_conversion)
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{
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static const struct {
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enum brw_reg_type dst_type;
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enum brw_reg_type src_type;
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unsigned dst_stride;
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unsigned dst_subnr;
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bool expected_result_bdw;
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bool expected_result_chv_gen9;
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} inst[] = {
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#define INST_C(dst_type, src_type, dst_stride, dst_subnr, expected_result) \
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{ \
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BRW_REGISTER_TYPE_##dst_type, \
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BRW_REGISTER_TYPE_##src_type, \
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BRW_HORIZONTAL_STRIDE_##dst_stride, \
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dst_subnr, \
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expected_result, \
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expected_result, \
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}
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#define INST_S(dst_type, src_type, dst_stride, dst_subnr, \
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expected_result_bdw, expected_result_chv_gen9) \
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{ \
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BRW_REGISTER_TYPE_##dst_type, \
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BRW_REGISTER_TYPE_##src_type, \
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BRW_HORIZONTAL_STRIDE_##dst_stride, \
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dst_subnr, \
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expected_result_bdw, \
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expected_result_chv_gen9, \
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}
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/* MOV to half-float destination */
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INST_C(HF, B, 1, 0, false),
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INST_C(HF, W, 1, 0, false),
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INST_C(HF, HF, 1, 0, true),
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INST_C(HF, HF, 1, 2, true),
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INST_C(HF, D, 1, 0, false),
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INST_S(HF, F, 1, 0, false, true),
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INST_C(HF, Q, 1, 0, false),
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INST_C(HF, B, 2, 0, true),
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INST_C(HF, B, 2, 2, false),
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INST_C(HF, W, 2, 0, true),
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INST_C(HF, W, 2, 2, false),
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INST_C(HF, HF, 2, 0, true),
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INST_C(HF, HF, 2, 2, true),
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INST_C(HF, D, 2, 0, true),
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INST_C(HF, D, 2, 2, false),
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INST_C(HF, F, 2, 0, true),
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INST_S(HF, F, 2, 2, false, true),
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INST_C(HF, Q, 2, 0, false),
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INST_C(HF, DF, 2, 0, false),
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INST_C(HF, B, 4, 0, false),
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INST_C(HF, W, 4, 0, false),
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INST_C(HF, HF, 4, 0, true),
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INST_C(HF, HF, 4, 2, true),
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INST_C(HF, D, 4, 0, false),
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INST_C(HF, F, 4, 0, false),
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INST_C(HF, Q, 4, 0, false),
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INST_C(HF, DF, 4, 0, false),
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/* MOV from half-float source */
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INST_C( B, HF, 1, 0, false),
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INST_C( W, HF, 1, 0, false),
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INST_C( D, HF, 1, 0, true),
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INST_C( D, HF, 1, 4, true),
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INST_C( F, HF, 1, 0, true),
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INST_C( F, HF, 1, 4, true),
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INST_C( Q, HF, 1, 0, false),
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INST_C(DF, HF, 1, 0, false),
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INST_C( B, HF, 2, 0, false),
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INST_C( W, HF, 2, 0, true),
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INST_C( W, HF, 2, 2, false),
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INST_C( D, HF, 2, 0, false),
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INST_C( F, HF, 2, 0, true),
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INST_C( B, HF, 4, 0, true),
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INST_C( B, HF, 4, 1, false),
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INST_C( W, HF, 4, 0, false),
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#undef INST_C
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#undef INST_S
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};
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if (devinfo.gen < 8)
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return;
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for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
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if (!devinfo.has_64bit_types &&
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(type_sz(inst[i].src_type) == 8 || type_sz(inst[i].dst_type) == 8)) {
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continue;
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}
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brw_MOV(p, retype(g0, inst[i].dst_type), retype(g0, inst[i].src_type));
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brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4);
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brw_inst_set_dst_hstride(&devinfo, last_inst, inst[i].dst_stride);
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brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, inst[i].dst_subnr);
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if (inst[i].src_type == BRW_REGISTER_TYPE_B) {
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brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
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brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_2);
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brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
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} else {
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brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
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brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
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brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
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}
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if (devinfo.is_cherryview || devinfo.gen >= 9)
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EXPECT_EQ(inst[i].expected_result_chv_gen9, validate(p));
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else
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EXPECT_EQ(inst[i].expected_result_bdw, validate(p));
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, vector_immediate_destination_alignment)
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TEST_P(validation_test, vector_immediate_destination_alignment)
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{
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{
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static const struct {
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static const struct {
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