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gallium: add PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE to skip util_range lock

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u_upload_mgr sets it, so that util_range_add can skip the lock.

The time spent in tc_transfer_flush_region decreases from 0.8% to 0.2%
in torcs on radeonsi.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Marek Olšák
2019-09-25 21:38:40 -04:00
parent 59dd4dafb5
commit 732ea0b213
39 changed files with 84 additions and 73 deletions
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4
src/gallium/drivers/iris/iris_blit.c
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@@ -453,7 +453,7 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
tex_cache_flush_hack(batch, src_fmt.fmt, src_res->surf.format);
if (dst_res->base.target == PIPE_BUFFER)
util_range_add(&dst_res->valid_buffer_range, dst_x0, dst_x1);
util_range_add(&dst_res->base, &dst_res->valid_buffer_range, dst_x0, dst_x1);
struct blorp_batch blorp_batch;
blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
@@ -577,7 +577,7 @@ iris_copy_region(struct blorp_context *blorp,
tex_cache_flush_hack(batch, ISL_FORMAT_UNSUPPORTED, src_res->surf.format);
if (dst->target == PIPE_BUFFER)
util_range_add(&dst_res->valid_buffer_range, dstx, dstx + src_box->width);
util_range_add(&dst_res->base, &dst_res->valid_buffer_range, dstx, dstx + src_box->width);
if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
struct blorp_address src_addr = {