ac/nir,radv,radeonsi: legacy vs use ac_nir_export_(position|parameter)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

src/amd/common/ac_nir.c

@@ -602,8 +602,8 @@ gather_outputs(nir_builder *b, nir_function_impl *impl, struct shader_outputs *o
     * - 64-bit outputs are lowered
     * - no indirect indexing is present
     */
-   nir_foreach_block(block, impl) {
+   nir_foreach_block (block, impl) {
-      nir_foreach_instr (instr, block) {
+      nir_foreach_instr_safe (instr, block) {
          if (instr->type != nir_instr_type_intrinsic)
             continue;
 
@@ -627,12 +627,23 @@ gather_outputs(nir_builder *b, nir_function_impl *impl, struct shader_outputs *o
             if (output_type)
                output_type[comp] = type;
          }
+
+         /* remove all store output instruction */
+         nir_instr_remove(instr);
       }
    }
 }
 
 void
-ac_nir_lower_legacy_vs(nir_shader *nir, int primitive_id_location, bool disable_streamout)
+ac_nir_lower_legacy_vs(nir_shader *nir,
+                       enum amd_gfx_level gfx_level,
+                       uint32_t clip_cull_mask,
+                       const uint8_t *param_offsets,
+                       bool has_param_exports,
+                       bool export_primitive_id,
+                       bool disable_streamout,
+                       bool kill_pointsize,
+                       bool force_vrs)
 {
    nir_function_impl *impl = nir_shader_get_entrypoint(nir);
    nir_metadata preserved = nir_metadata_block_index | nir_metadata_dominance;
@@ -641,43 +652,46 @@ ac_nir_lower_legacy_vs(nir_shader *nir, int primitive_id_location, bool disable_
    nir_builder_init(&b, impl);
    b.cursor = nir_after_cf_list(&impl->body);
 
-   if (primitive_id_location >= 0) {
+   nir_alu_type output_types_16bit_lo[16][4];
+   nir_alu_type output_types_16bit_hi[16][4];
+   struct shader_outputs outputs = {
+      .type_16bit_lo = output_types_16bit_lo,
+      .type_16bit_hi = output_types_16bit_hi,
+   };
+   gather_outputs(&b, impl, &outputs);
+
+   if (export_primitive_id) {
       /* When the primitive ID is read by FS, we must ensure that it's exported by the previous
        * vertex stage because it's implicit for VS or TES (but required by the Vulkan spec for GS
        * or MS).
        */
-      nir_variable *var = nir_variable_create(nir, nir_var_shader_out, glsl_int_type(), NULL);
+      outputs.data[VARYING_SLOT_PRIMITIVE_ID][0] = nir_load_primitive_id(&b);
-      var->data.location = VARYING_SLOT_PRIMITIVE_ID;
-      var->data.interpolation = INTERP_MODE_NONE;
-      var->data.driver_location = primitive_id_location;
-
-      nir_store_output(
-         &b, nir_load_primitive_id(&b), nir_imm_int(&b, 0), .base = primitive_id_location,
-         .src_type = nir_type_int32,
-         .io_semantics = (nir_io_semantics){.location = var->data.location, .num_slots = 1});
 
       /* Update outputs_written to reflect that the pass added a new output. */
       nir->info.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_ID);
    }
 
    if (!disable_streamout && nir->xfb_info) {
-      /* 26.1. Transform Feedback of Vulkan 1.3.229 spec:
-       * > The size of each component of an output variable must be at least 32-bits.
-       * We lower 64-bit outputs.
-       */
-      nir_alu_type output_types_16bit_lo[16][4];
-      nir_alu_type output_types_16bit_hi[16][4];
-      struct shader_outputs outputs = {
-         .type_16bit_lo = output_types_16bit_lo,
-         .type_16bit_hi = output_types_16bit_hi,
-      };
-      gather_outputs(&b, impl, &outputs);
-
       emit_streamout(&b, 0, nir->xfb_info, &outputs);
       preserved = nir_metadata_none;
    }
 
-   nir_export_vertex_amd(&b);
+   uint64_t export_outputs = nir->info.outputs_written;
+   if (kill_pointsize)
+      export_outputs &= ~VARYING_BIT_PSIZ;
+
+   ac_nir_export_position(&b, gfx_level, clip_cull_mask, !has_param_exports,
+                          force_vrs, export_outputs, outputs.data);
+
+   if (has_param_exports) {
+      ac_nir_export_parameter(&b, param_offsets,
+                              nir->info.outputs_written,
+                              nir->info.outputs_written_16bit,
+                              outputs.data,
+                              outputs.data_16bit_lo,
+                              outputs.data_16bit_hi);
+   }
+
    nir_metadata_preserve(impl, preserved);
 }
 

src/amd/common/ac_nir.h

@@ -238,7 +238,15 @@ ac_nir_create_gs_copy_shader(const nir_shader *gs_nir,
                              ac_nir_gs_output_info *output_info);
 
 void
-ac_nir_lower_legacy_vs(nir_shader *nir, int primitive_id_location, bool disable_streamout);
+ac_nir_lower_legacy_vs(nir_shader *nir,
+                       enum amd_gfx_level gfx_level,
+                       uint32_t clip_cull_mask,
+                       const uint8_t *param_offsets,
+                       bool has_param_exports,
+                       bool export_primitive_id,
+                       bool disable_streamout,
+                       bool kill_pointsize,
+                       bool force_vrs);
 
 bool
 ac_nir_gs_shader_query(nir_builder *b,

src/amd/vulkan/radv_pipeline.c

@@ -3305,7 +3305,12 @@ radv_postprocess_nir(struct radv_pipeline *pipeline,
    if (stage->stage == last_vgt_api_stage && !lowered_ngg) {
       if (stage->stage != MESA_SHADER_GEOMETRY) {
          NIR_PASS_V(stage->nir, ac_nir_lower_legacy_vs,
-                    stage->info.outinfo.export_prim_id ? VARYING_SLOT_PRIMITIVE_ID : -1, false);
+                    gfx_level,
+                    stage->info.outinfo.clip_dist_mask | stage->info.outinfo.cull_dist_mask,
+                    stage->info.outinfo.vs_output_param_offset,
+                    stage->info.outinfo.param_exports,
+                    stage->info.outinfo.export_prim_id,
+                    false, false, false);
 
       } else {
          ac_nir_gs_output_info gs_out_info = {

src/gallium/drivers/radeonsi/si_shader.c

@@ -1945,11 +1945,19 @@ struct nir_shader *si_get_nir_shader(struct si_shader *shader,
          opt_offsets = true;
       } else if (sel->stage == MESA_SHADER_VERTEX || sel->stage == MESA_SHADER_TESS_EVAL) {
          /* Lower last VGT none-NGG VS/TES shader stage. */
-         int primitive_id_location =
+         unsigned clip_cull_mask =
-            shader->key.ge.mono.u.vs_export_prim_id ? sel->info.num_outputs : -1;
+            (sel->info.clipdist_mask & ~key->ge.opt.kill_clip_distances) |
+            sel->info.culldist_mask;
 
-         NIR_PASS_V(nir, ac_nir_lower_legacy_vs, primitive_id_location,
+         NIR_PASS_V(nir, ac_nir_lower_legacy_vs,
-                    key->ge.opt.remove_streamout);
+                    sel->screen->info.gfx_level,
+                    clip_cull_mask,
+                    shader->info.vs_output_param_offset,
+                    shader->info.nr_param_exports,
+                    shader->key.ge.mono.u.vs_export_prim_id,
+                    key->ge.opt.remove_streamout,
+                    key->ge.opt.kill_pointsize,
+                    sel->screen->options.vrs2x2);
       }
    } else if (is_legacy_gs) {
       NIR_PASS_V(nir, ac_nir_lower_legacy_gs, false, sel->screen->use_ngg, output_info);