OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/dev: Drop coherency from intel_device_info_pat_entry

Browse Source 
It is not used in run-time so we can drop from the struct.
It might have value as PAT entries documentation but that will be done
in the next patch.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29950>
This commit is contained in:
José Roberto de Souza
2024-06-27 14:57:57 -07:00
committed by Marge Bot
parent fa1129540a
commit 7295e09b53
3 changed files with 20 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
src/intel/dev/intel_device_info.c
View File

@@ -985,10 +985,10 @@ static const struct intel_device_info intel_device_info_ehl_2x4 = {
.simulator_id = 22, \
.max_eus_per_subslice = 16, \
.pat = { \
.cached_coherent = PAT_ENTRY(0, WB, 2WAY), \
.scanout = PAT_ENTRY(1, WC, NONE), \
.writeback_incoherent = PAT_ENTRY(0, WB, 2WAY), \
.writecombining = PAT_ENTRY(1, WC, NONE), \
.cached_coherent = PAT_ENTRY(0, WB), \
.scanout = PAT_ENTRY(1, WC), \
.writeback_incoherent = PAT_ENTRY(0, WB), \
.writecombining = PAT_ENTRY(1, WC), \
}, \
.cooperative_matrix_configurations = { \
{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT32, INTEL_CMAT_FLOAT32 }, \
@@ -1130,10 +1130,10 @@ static const struct intel_device_info intel_device_info_sg1 = {
.has_flat_ccs = true, \
/* There is no PAT table for DG2, using TGL ones */ \
.pat = { \
.cached_coherent = PAT_ENTRY(0, WB, 1WAY), \
.scanout = PAT_ENTRY(1, WC, NONE), \
.writeback_incoherent = PAT_ENTRY(0, WB, 2WAY), \
.writecombining = PAT_ENTRY(1, WC, NONE), \
.cached_coherent = PAT_ENTRY(0, WB), \
.scanout = PAT_ENTRY(1, WC), \
.writeback_incoherent = PAT_ENTRY(0, WB), \
.writecombining = PAT_ENTRY(1, WC), \
}
static const struct intel_device_info intel_device_info_dg2_g10 = {
@@ -1173,10 +1173,10 @@ static const struct intel_device_info intel_device_info_atsm_g11 = {
.has_mesh_shading = true, \
.has_ray_tracing = true, \
.pat = { \
.cached_coherent = PAT_ENTRY(3, WB, 1WAY), \
.scanout = PAT_ENTRY(1, WC, NONE), \
.writeback_incoherent = PAT_ENTRY(0, WB, NONE), \
.writecombining = PAT_ENTRY(1, WC, NONE), \
.cached_coherent = PAT_ENTRY(3, WB), \
.scanout = PAT_ENTRY(1, WC), \
.writeback_incoherent = PAT_ENTRY(0, WB), \
.writecombining = PAT_ENTRY(1, WC), \
}
static const struct intel_device_info intel_device_info_mtl_u = {
@@ -1214,11 +1214,11 @@ static const struct intel_device_info intel_device_info_arl_h = {
.has_ray_tracing = true, \
.has_indirect_unroll = true, \
.pat = { \
.cached_coherent = PAT_ENTRY(1, WB, 1WAY), \
.scanout = PAT_ENTRY(6, WC, NONE), \
.writeback_incoherent = PAT_ENTRY(0, WB, NONE), \
.writecombining = PAT_ENTRY(6, WC, NONE), \
.compressed = PAT_ENTRY(11, WC, NONE) \
.cached_coherent = PAT_ENTRY(1, WB), \
.scanout = PAT_ENTRY(6, WC), \
.writeback_incoherent = PAT_ENTRY(0, WB), \
.writecombining = PAT_ENTRY(6, WC), \
.compressed = PAT_ENTRY(11, WC) \
}, \
.cooperative_matrix_configurations = { \
{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 16, 16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT32, INTEL_CMAT_FLOAT32 }, \

5
src/intel/dev/intel_device_info.h
View File

@@ -64,11 +64,10 @@ extern "C" {
#define intel_device_info_is_mtl_or_arl(devinfo) \
(intel_device_info_is_mtl(devinfo) || intel_device_info_is_arl(devinfo))
#define PAT_ENTRY(index_, mmap_, coh_) \
#define PAT_ENTRY(index_, mmap_) \
{ \
.index = index_, \
.mmap = INTEL_DEVICE_INFO_MMAP_MODE_##mmap_, \
.coherency = INTEL_DEVICE_INFO_COHERENCY_MODE_##coh_ \
.mmap = INTEL_DEVICE_INFO_MMAP_MODE_##mmap_ \
}
#ifdef GFX_VER

10
src/intel/dev/intel_device_info.py
View File

@@ -147,20 +147,12 @@ Enum("intel_device_info_mmap_mode",
"INTEL_DEVICE_INFO_MMAP_MODE_WB"
])
Enum("intel_device_info_coherency_mode",
[EnumValue("INTEL_DEVICE_INFO_COHERENCY_MODE_NONE", value=0),
EnumValue("INTEL_DEVICE_INFO_COHERENCY_MODE_1WAY", comment="CPU caches are snooped by GPU"),
EnumValue("INTEL_DEVICE_INFO_COHERENCY_MODE_2WAY",
comment="Fully coherent between GPU and CPU")
])
Struct("intel_device_info_pat_entry",
[Member("uint8_t", "index"),
Member("intel_device_info_mmap_mode", "mmap",
comment=dedent("""\
This tells KMD what caching mode the CPU mapping should use.
It has nothing to do with any PAT cache modes.""")),
Member("intel_device_info_coherency_mode", "coherency")])
It has nothing to do with any PAT cache modes."""))])
Enum("intel_cmat_scope",
[EnumValue("INTEL_CMAT_SCOPE_NONE", value=0),