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intel/fs: Rely on undocumented unrestricted regioning for 32x16-bit integer multiply.

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Even though the hardware spec claims that any "integer DWord multiply"
operation is affected by the regioning restrictions of CHV/BXT/GLK,
this is inconsistent with the behavior of the simulator and with
empirical evidence -- Return false from has_dst_aligned_region_restriction()
for such instructions as a micro-optimization.

Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Francisco Jerez
2019-01-18 11:38:17 -08:00
parent e03be78252
commit 7272fe9c08
1 changed files with 11 additions and 3 deletions
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14
src/intel/compiler/brw_ir_fs.h
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@@ -542,11 +542,19 @@ has_dst_aligned_region_restriction(const gen_device_info *devinfo,
const fs_inst *inst)
{
const brw_reg_type exec_type = get_exec_type(inst);
const bool is_int_multiply = !brw_reg_type_is_floating_point(exec_type) &&
(inst->opcode == BRW_OPCODE_MUL || inst->opcode == BRW_OPCODE_MAD);
/* Even though the hardware spec claims that "integer DWord multiply"
* operations are restricted, empirical evidence and the behavior of the
* simulator suggest that only 32x32-bit integer multiplication is
* restricted.
*/
const bool is_dword_multiply = !brw_reg_type_is_floating_point(exec_type) &&
((inst->opcode == BRW_OPCODE_MUL &&
MIN2(type_sz(inst->src[0].type), type_sz(inst->src[1].type)) >= 4) ||
(inst->opcode == BRW_OPCODE_MAD &&
MIN2(type_sz(inst->src[1].type), type_sz(inst->src[2].type)) >= 4));
if (type_sz(inst->dst.type) > 4 || type_sz(exec_type) > 4 ||
(type_sz(exec_type) == 4 && is_int_multiply))
(type_sz(exec_type) == 4 && is_dword_multiply))
return devinfo->is_cherryview || gen_device_info_is_9lp(devinfo);
else
return false;