vc4: Sync with kernel changes to relax BCL versus RCL validation.
There was no reason to tie the two packets' values together.
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@@ -589,21 +589,6 @@ validate_tile_rendering_mode_config(VALIDATE_ARGS)
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exec->fb_width = *(uint16_t *)(untrusted + 4);
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exec->fb_height = *(uint16_t *)(untrusted + 6);
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/* Make sure that the fb width/height matches the binning config -- we
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* rely on being able to interchange these for various assertions.
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* (Within a tile, loads and stores will be clipped to the
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* width/height, but we allow load/storing to any binned tile).
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*/
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if (exec->fb_width <= (exec->bin_tiles_x - 1) * 64 ||
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exec->fb_width > exec->bin_tiles_x * 64 ||
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exec->fb_height <= (exec->bin_tiles_y - 1) * 64 ||
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exec->fb_height > exec->bin_tiles_y * 64) {
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DRM_ERROR("bin config %dx%d doesn't match FB %dx%d\n",
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exec->bin_tiles_x, exec->bin_tiles_y,
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exec->fb_width, exec->fb_height);
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return -EINVAL;
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}
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flags = *(uint16_t *)(untrusted + 8);
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if ((flags & VC4_RENDER_CONFIG_FORMAT_MASK) ==
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VC4_RENDER_CONFIG_FORMAT_RGBA8888) {
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@@ -632,13 +617,9 @@ validate_tile_coordinates(VALIDATE_ARGS)
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uint8_t tile_x = *(uint8_t *)(untrusted + 0);
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uint8_t tile_y = *(uint8_t *)(untrusted + 1);
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if (tile_x >= exec->bin_tiles_x ||
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tile_y >= exec->bin_tiles_y) {
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DRM_ERROR("Tile coordinates %d,%d > bin config %d,%d\n",
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tile_x,
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tile_y,
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exec->bin_tiles_x,
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exec->bin_tiles_y);
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if (tile_x * 64 >= exec->fb_width || tile_y * 64 >= exec->fb_height) {
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DRM_ERROR("Tile coordinates %d,%d > render config %dx%d\n",
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tile_x, tile_y, exec->fb_width, exec->fb_height);
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return -EINVAL;
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}
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