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r600: fix flat shading

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Set the flat shading bit on the appropriate PS input
depending on the type of attribute it is.  The VS output
and PS input routing should probably be made more dynamic
at some point.  We may want to use semantic ids to make
it easier.
This commit is contained in:
Alex Deucher
2009-07-28 16:58:41 -04:00
parent dbdb3952c1
commit 719abd7fc0
4 changed files with 60 additions and 81 deletions
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44
src/mesa/drivers/dri/r600/r700_chip.c
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@@ -213,39 +213,6 @@ GLboolean r700InitChipObject(context_t *context)
LINK_STATES(SPI_VS_OUT_ID_8); LINK_STATES(SPI_VS_OUT_ID_8);
LINK_STATES(SPI_VS_OUT_ID_9); LINK_STATES(SPI_VS_OUT_ID_9);
LINK_STATES(SPI_PS_INPUT_CNTL_0);
LINK_STATES(SPI_PS_INPUT_CNTL_1);
LINK_STATES(SPI_PS_INPUT_CNTL_2);
LINK_STATES(SPI_PS_INPUT_CNTL_3);
LINK_STATES(SPI_PS_INPUT_CNTL_4);
LINK_STATES(SPI_PS_INPUT_CNTL_5);
LINK_STATES(SPI_PS_INPUT_CNTL_6);
LINK_STATES(SPI_PS_INPUT_CNTL_7);
LINK_STATES(SPI_PS_INPUT_CNTL_8);
LINK_STATES(SPI_PS_INPUT_CNTL_9);
LINK_STATES(SPI_PS_INPUT_CNTL_10);
LINK_STATES(SPI_PS_INPUT_CNTL_11);
LINK_STATES(SPI_PS_INPUT_CNTL_12);
LINK_STATES(SPI_PS_INPUT_CNTL_13);
LINK_STATES(SPI_PS_INPUT_CNTL_14);
LINK_STATES(SPI_PS_INPUT_CNTL_15);
LINK_STATES(SPI_PS_INPUT_CNTL_16);
LINK_STATES(SPI_PS_INPUT_CNTL_17);
LINK_STATES(SPI_PS_INPUT_CNTL_18);
LINK_STATES(SPI_PS_INPUT_CNTL_19);
LINK_STATES(SPI_PS_INPUT_CNTL_20);
LINK_STATES(SPI_PS_INPUT_CNTL_21);
LINK_STATES(SPI_PS_INPUT_CNTL_22);
LINK_STATES(SPI_PS_INPUT_CNTL_23);
LINK_STATES(SPI_PS_INPUT_CNTL_24);
LINK_STATES(SPI_PS_INPUT_CNTL_25);
LINK_STATES(SPI_PS_INPUT_CNTL_26);
LINK_STATES(SPI_PS_INPUT_CNTL_27);
LINK_STATES(SPI_PS_INPUT_CNTL_28);
LINK_STATES(SPI_PS_INPUT_CNTL_29);
LINK_STATES(SPI_PS_INPUT_CNTL_30);
LINK_STATES(SPI_PS_INPUT_CNTL_31);
LINK_STATES(SPI_VS_OUT_CONFIG); LINK_STATES(SPI_VS_OUT_CONFIG);
LINK_STATES(SPI_THREAD_GROUPING); LINK_STATES(SPI_THREAD_GROUPING);
LINK_STATES(SPI_PS_IN_CONTROL_0); LINK_STATES(SPI_PS_IN_CONTROL_0);
@@ -435,12 +402,21 @@ GLboolean r700SendContextStates(context_t *context)
}; };
END_BATCH(); END_BATCH();
}; };
/* todo:
* - split this into a separate function?
* - only emit the ones we use
*/
BEGIN_BATCH_NO_AUTOSTATE(2 + R700_MAX_SHADER_EXPORTS);
R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
END_BATCH();
COMMIT_BATCH(); COMMIT_BATCH();
return GL_TRUE; return GL_TRUE;
} }
GLboolean r700SendDepthTargetState(context_t *context, int id) GLboolean r700SendDepthTargetState(context_t *context, int id)
{ {
R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);

33
src/mesa/drivers/dri/r600/r700_chip.h
View File

@@ -455,38 +455,7 @@ typedef struct _R700_CHIP_CONTEXT
union UINT_FLOAT SQ_VTX_SEMANTIC_30 ; /* 0xA0FE */ union UINT_FLOAT SQ_VTX_SEMANTIC_30 ; /* 0xA0FE */
union UINT_FLOAT SQ_VTX_SEMANTIC_31 ; /* 0xA0FF */ union UINT_FLOAT SQ_VTX_SEMANTIC_31 ; /* 0xA0FF */
union UINT_FLOAT SPI_PS_INPUT_CNTL_0 ; /* 0xA191 */ union UINT_FLOAT SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS];
union UINT_FLOAT SPI_PS_INPUT_CNTL_1 ; /* 0xA192 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_2 ; /* 0xA193 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_3 ; /* 0xA194 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_4 ; /* 0xA195 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_5 ; /* 0xA196 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_6 ; /* 0xA197 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_7 ; /* 0xA198 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_8 ; /* 0xA199 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_9 ; /* 0xA19A */
union UINT_FLOAT SPI_PS_INPUT_CNTL_10 ; /* 0xA19B */
union UINT_FLOAT SPI_PS_INPUT_CNTL_11 ; /* 0xA19C */
union UINT_FLOAT SPI_PS_INPUT_CNTL_12 ; /* 0xA19D */
union UINT_FLOAT SPI_PS_INPUT_CNTL_13 ; /* 0xA19E */
union UINT_FLOAT SPI_PS_INPUT_CNTL_14 ; /* 0xA19F */
union UINT_FLOAT SPI_PS_INPUT_CNTL_15 ; /* 0xA1A0 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_16 ; /* 0xA1A1 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_17 ; /* 0xA1A2 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_18 ; /* 0xA1A3 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_19 ; /* 0xA1A4 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_20 ; /* 0xA1A5 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_21 ; /* 0xA1A6 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_22 ; /* 0xA1A7 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_23 ; /* 0xA1A8 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_24 ; /* 0xA1A9 */
union UINT_FLOAT SPI_PS_INPUT_CNTL_25 ; /* 0xA1AA */
union UINT_FLOAT SPI_PS_INPUT_CNTL_26 ; /* 0xA1AB */
union UINT_FLOAT SPI_PS_INPUT_CNTL_27 ; /* 0xA1AC */
union UINT_FLOAT SPI_PS_INPUT_CNTL_28 ; /* 0xA1AD */
union UINT_FLOAT SPI_PS_INPUT_CNTL_29 ; /* 0xA1AE */
union UINT_FLOAT SPI_PS_INPUT_CNTL_30 ; /* 0xA1AF */
union UINT_FLOAT SPI_PS_INPUT_CNTL_31 ; /* 0xA1B0 */
// shaders // shaders
PS_STATE_STRUCT ps; PS_STATE_STRUCT ps;

58
src/mesa/drivers/dri/r600/r700_fragprog.c
View File

@@ -255,20 +255,20 @@ void * r700GetActiveFpShaderBo(GLcontext * ctx)
GLboolean r700SetupFragmentProgram(GLcontext * ctx) GLboolean r700SetupFragmentProgram(GLcontext * ctx)
{ {
context_t *context = R700_CONTEXT(ctx); context_t *context = R700_CONTEXT(ctx);
BATCH_LOCALS(&context->radeon); BATCH_LOCALS(&context->radeon);
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
struct r700_fragment_program *fp = (struct r700_fragment_program *) struct r700_fragment_program *fp = (struct r700_fragment_program *)
(ctx->FragmentProgram._Current); (ctx->FragmentProgram._Current);
r700_AssemblerBase *pAsm = &(fp->r700AsmCode);
struct gl_fragment_program *mesa_fp = &(fp->mesa_program);
struct gl_program_parameter_list *paramList; struct gl_program_parameter_list *paramList;
unsigned int unNumParamData; unsigned int unNumParamData;
unsigned int ui; unsigned int ui, i;
unsigned int unNumOfReg; unsigned int unNumOfReg;
unsigned int unBit;
if(GL_FALSE == fp->loaded) if(GL_FALSE == fp->loaded)
{ {
if(fp->r700Shader.bNeedsAssembly == GL_TRUE) if(fp->r700Shader.bNeedsAssembly == GL_TRUE)
@@ -277,11 +277,11 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
} }
/* Load fp to gpu */ /* Load fp to gpu */
r600EmitShader(ctx, r600EmitShader(ctx,
&(fp->shaderbo), &(fp->shaderbo),
(GLvoid *)(fp->r700Shader.pProgram), (GLvoid *)(fp->r700Shader.pProgram),
fp->r700Shader.uShaderBinaryDWORDSize, fp->r700Shader.uShaderBinaryDWORDSize,
"FS"); "FS");
fp->loaded = GL_TRUE; fp->loaded = GL_TRUE;
} }
@@ -362,6 +362,46 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
COMMIT_BATCH(); COMMIT_BATCH();
} }
// emit ps input map
unBit = 1 << FRAG_ATTRIB_COL0;
if(mesa_fp->Base.InputsRead & unBit)
{
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0];
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
SEMANTIC_shift, SEMANTIC_mask);
if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
else
CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
}
unBit = 1 << FRAG_ATTRIB_COL1;
if(mesa_fp->Base.InputsRead & unBit)
{
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1];
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
SEMANTIC_shift, SEMANTIC_mask);
if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
else
CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
}
for(i=0; i<8; i++)
{
unBit = 1 << (FRAG_ATTRIB_TEX0 + i);
if(mesa_fp->Base.InputsRead & unBit)
{
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i];
SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
SEMANTIC_shift, SEMANTIC_mask);
CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
}
}
return GL_TRUE; return GL_TRUE;
} }

6
src/mesa/drivers/dri/r600/r700_state.c
View File

@@ -824,11 +824,9 @@ static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
switch (mode) { switch (mode) {
case GL_FLAT: case GL_FLAT:
SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit); SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
//SETbit(r700->SPI_PS_INPUT_CNTL_0.u32All, FLAT_SHADE_bit);
break; break;
case GL_SMOOTH: case GL_SMOOTH:
CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit); CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
//CLEARbit(r700->SPI_PS_INPUT_CNTL_0.u32All, FLAT_SHADE_bit);
break; break;
default: default:
return; return;
@@ -1675,10 +1673,6 @@ void r700InitState(GLcontext * ctx) //-------------------
r700->SPI_VS_OUT_ID_0.u32All = 0x03020100; r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
r700->SPI_VS_OUT_ID_1.u32All = 0x07060504; r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800;
r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801;
r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802;
r700->SPI_THREAD_GROUPING.u32All = 0; r700->SPI_THREAD_GROUPING.u32All = 0;
if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770) if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask); SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);