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anv: Use 3DSTATE_URB_ALLOC_* instructions

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Use 3DSTATE_URB_ALLOC_* instruction to program URB for multislice device
config.

In case only one slice is available in the device, SliceN fields will be
ignored by HW.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32736>
This commit is contained in:
Sagar Ghuge
2023-09-21 22:03:55 -07:00
committed by Marge Bot
parent 604a384e97
commit 710624fcc0
3 changed files with 57 additions and 0 deletions
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11
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -6421,12 +6421,23 @@ genX(urb_workaround)(struct anv_cmd_buffer *cmd_buffer,
if (intel_urb_setup_changed(urb_cfg, current, MESA_SHADER_TESS_EVAL) &&
current->size[0] != 0) {
for (int i = 0; i <= MESA_SHADER_GEOMETRY; i++) {
#if GFX_VER >= 12
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_URB_ALLOC_VS), urb) {
urb._3DCommandSubOpcode += i;
urb.VSURBEntryAllocationSize = current->size[i] - 1;
urb.VSURBStartingAddressSlice0 = current->start[i];
urb.VSURBStartingAddressSliceN = current->start[i];
urb.VSNumberofURBEntriesSlice0 = i == 0 ? 256 : 0;
urb.VSNumberofURBEntriesSliceN = i == 0 ? 256 : 0;
}
#else
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_URB_VS), urb) {
urb._3DCommandSubOpcode += i;
urb.VSURBStartingAddress = current->start[i];
urb.VSURBEntryAllocationSize = current->size[i] - 1;
urb.VSNumberofURBEntries = i == 0 ? 256 : 0;
}
#endif
}
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.HDCPipelineFlushEnable = true;

6
src/intel/vulkan/genX_init_state.c
View File

@@ -1491,9 +1491,15 @@ genX(apply_task_urb_workaround)(struct anv_cmd_buffer *cmd_buffer)
return;
for (int i = 0; i <= MESA_SHADER_GEOMETRY; i++) {
#if GFX_VER >= 12
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_URB_ALLOC_VS), urb) {
urb._3DCommandSubOpcode += i;
}
#else
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_URB_VS), urb) {
urb._3DCommandSubOpcode += i;
}
#endif
}
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_URB_ALLOC_MESH), zero);

40
src/intel/vulkan/genX_pipeline.c
View File

@@ -456,12 +456,23 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
if (intel_urb_setup_changed(urb_cfg_in, urb_cfg_out,
MESA_SHADER_TESS_EVAL) && urb_cfg_in->size[0] != 0) {
for (int i = 0; i <= MESA_SHADER_GEOMETRY; i++) {
#if GFX_VER >= 12
anv_batch_emit(batch, GENX(3DSTATE_URB_ALLOC_VS), urb) {
urb._3DCommandSubOpcode += i;
urb.VSURBEntryAllocationSize = urb_cfg_in->size[i] - 1;
urb.VSURBStartingAddressSlice0 = urb_cfg_in->start[i];
urb.VSURBStartingAddressSliceN = urb_cfg_in->start[i];
urb.VSNumberofURBEntriesSlice0 = i == 0 ? 256 : 0;
urb.VSNumberofURBEntriesSliceN = i == 0 ? 256 : 0;
}
#else
anv_batch_emit(batch, GENX(3DSTATE_URB_VS), urb) {
urb._3DCommandSubOpcode += i;
urb.VSURBStartingAddress = urb_cfg_in->start[i];
urb.VSURBEntryAllocationSize = urb_cfg_in->size[i] - 1;
urb.VSNumberofURBEntries = i == 0 ? 256 : 0;
}
#endif
}
genx_batch_emit_pipe_control(batch, device->info, _3D,
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT);
@@ -469,13 +480,25 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
#endif
for (int i = 0; i <= MESA_SHADER_GEOMETRY; i++) {
#if GFX_VER >= 12
anv_batch_emit(batch, GENX(3DSTATE_URB_ALLOC_VS), urb) {
urb._3DCommandSubOpcode += i;
urb.VSURBEntryAllocationSize = urb_cfg_out->size[i] - 1;
urb.VSURBStartingAddressSlice0 = urb_cfg_out->start[i];
urb.VSURBStartingAddressSliceN = urb_cfg_out->start[i];
urb.VSNumberofURBEntriesSlice0 = urb_cfg_out->entries[i];
urb.VSNumberofURBEntriesSliceN = urb_cfg_out->entries[i];
}
#else
anv_batch_emit(batch, GENX(3DSTATE_URB_VS), urb) {
urb._3DCommandSubOpcode += i;
urb.VSURBStartingAddress = urb_cfg_out->start[i];
urb.VSURBEntryAllocationSize = urb_cfg_out->size[i] - 1;
urb.VSNumberofURBEntries = urb_cfg_out->entries[i];
}
#endif
}
#if GFX_VERx10 >= 125
if (device->vk.enabled_extensions.EXT_mesh_shader) {
anv_batch_emit(batch, GENX(3DSTATE_URB_ALLOC_MESH), zero);
@@ -503,9 +526,15 @@ emit_urb_setup_mesh(struct anv_graphics_pipeline *pipeline,
/* Zero out the primitive pipeline URB allocations. */
for (int i = 0; i <= MESA_SHADER_GEOMETRY; i++) {
#if GFX_VER >= 12
anv_pipeline_emit(pipeline, final.urb, GENX(3DSTATE_URB_ALLOC_VS), urb) {
urb._3DCommandSubOpcode += i;
}
#else
anv_pipeline_emit(pipeline, final.urb, GENX(3DSTATE_URB_VS), urb) {
urb._3DCommandSubOpcode += i;
}
#endif
}
anv_pipeline_emit(pipeline, final.urb, GENX(3DSTATE_URB_ALLOC_TASK), urb) {
@@ -563,12 +592,23 @@ emit_urb_setup(struct anv_graphics_pipeline *pipeline,
&constrained);
for (int i = 0; i <= MESA_SHADER_GEOMETRY; i++) {
#if GFX_VER >= 12
anv_pipeline_emit(pipeline, final.urb, GENX(3DSTATE_URB_ALLOC_VS), urb) {
urb._3DCommandSubOpcode += i;
urb.VSURBEntryAllocationSize = pipeline->urb_cfg.size[i] - 1;
urb.VSURBStartingAddressSlice0 = pipeline->urb_cfg.start[i];
urb.VSURBStartingAddressSliceN = pipeline->urb_cfg.start[i];
urb.VSNumberofURBEntriesSlice0 = pipeline->urb_cfg.entries[i];
urb.VSNumberofURBEntriesSliceN = pipeline->urb_cfg.entries[i];
}
#else
anv_pipeline_emit(pipeline, final.urb, GENX(3DSTATE_URB_VS), urb) {
urb._3DCommandSubOpcode += i;
urb.VSURBStartingAddress = pipeline->urb_cfg.start[i];
urb.VSURBEntryAllocationSize = pipeline->urb_cfg.size[i] - 1;
urb.VSNumberofURBEntries = pipeline->urb_cfg.entries[i];
}
#endif
}
#if GFX_VERx10 >= 125