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radv: fix the late scissor emission workaround with ESO on GFX9

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graphics_pipeline is NULL when ESO is used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27236>
This commit is contained in:
Samuel Pitoiset
2024-01-19 10:28:44 +01:00
committed by Marge Bot
parent 411e23e193
commit 70c288558a
1 changed files with 19 additions and 19 deletions
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38
src/amd/vulkan/radv_cmd_buffer.c
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@@ -8745,6 +8745,24 @@ radv_emit_indirect_draw_packets(struct radv_cmd_buffer *cmd_buffer, const struct
} }
} }
static uint64_t
radv_get_needed_dynamic_states(struct radv_cmd_buffer *cmd_buffer)
{
uint64_t dynamic_states = RADV_DYNAMIC_ALL;
if (cmd_buffer->state.graphics_pipeline)
return cmd_buffer->state.graphics_pipeline->needed_dynamic_state;
/* Clear unnecessary dynamic states for shader objects. */
if (!cmd_buffer->state.shaders[MESA_SHADER_TESS_CTRL])
dynamic_states &= ~RADV_DYNAMIC_PATCH_CONTROL_POINTS;
if (!cmd_buffer->state.shaders[MESA_SHADER_TESS_EVAL])
dynamic_states &= ~RADV_DYNAMIC_TESS_DOMAIN_ORIGIN;
dynamic_states &= ~RADV_DYNAMIC_FRAGMENT_SHADING_RATE;
return dynamic_states;
}
/* /*
* Vega and raven have a bug which triggers if there are multiple context * Vega and raven have a bug which triggers if there are multiple context
* register contexts active at the same time with different scissor values. * register contexts active at the same time with different scissor values.
@@ -8767,7 +8785,7 @@ radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer, const struct
if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer) if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
return true; return true;
uint64_t used_states = cmd_buffer->state.graphics_pipeline->needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL; uint64_t used_states = radv_get_needed_dynamic_states(cmd_buffer) | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
/* Index, vertex and streamout buffers don't change context regs. /* Index, vertex and streamout buffers don't change context regs.
* We assume that any other dirty flag causes context rolls. * We assume that any other dirty flag causes context rolls.
@@ -9058,24 +9076,6 @@ radv_emit_shaders(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_SHADERS; cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_SHADERS;
} }
static uint64_t
radv_get_needed_dynamic_states(struct radv_cmd_buffer *cmd_buffer)
{
uint64_t dynamic_states = RADV_DYNAMIC_ALL;
if (cmd_buffer->state.graphics_pipeline)
return cmd_buffer->state.graphics_pipeline->needed_dynamic_state;
/* Clear unnecessary dynamic states for shader objects. */
if (!cmd_buffer->state.shaders[MESA_SHADER_TESS_CTRL])
dynamic_states &= ~RADV_DYNAMIC_PATCH_CONTROL_POINTS;
if (!cmd_buffer->state.shaders[MESA_SHADER_TESS_EVAL])
dynamic_states &= ~RADV_DYNAMIC_TESS_DOMAIN_ORIGIN;
dynamic_states &= ~RADV_DYNAMIC_FRAGMENT_SHADING_RATE;
return dynamic_states;
}
static void static void
radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info) radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info)
{ {