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radv: do not use an user SGPR for the sample position offset

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We know the number of samples at compile time.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2018-06-19 14:25:48 +02:00
parent 20170865db
commit 70c1bee187
3 changed files with 30 additions and 40 deletions
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40
src/amd/vulkan/radv_nir_to_llvm.c
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@@ -81,7 +81,6 @@ struct radv_shader_context {
LLVMValueRef hs_ring_tess_offchip;
LLVMValueRef hs_ring_tess_factor;
LLVMValueRef sample_pos_offset;
LLVMValueRef persp_sample, persp_center, persp_centroid;
LLVMValueRef linear_sample, linear_center, linear_centroid;
@@ -1095,10 +1094,6 @@ static void create_function(struct radv_shader_context *ctx,
previous_stage, &user_sgpr_info,
&args, &desc_sets);
if (ctx->shader_info->info.ps.needs_sample_positions)
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->sample_pos_offset);
add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
@@ -1194,10 +1189,6 @@ static void create_function(struct radv_shader_context *ctx,
set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
break;
case MESA_SHADER_FRAGMENT:
if (ctx->shader_info->info.ps.needs_sample_positions) {
set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
&user_sgpr_idx, 1);
}
break;
default:
unreachable("Shader stage not implemented");
@@ -1627,6 +1618,30 @@ static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
return NULL;
}
static uint32_t
radv_get_sample_pos_offset(uint32_t num_samples)
{
uint32_t sample_pos_offset = 0;
switch (num_samples) {
case 2:
sample_pos_offset = 1;
break;
case 4:
sample_pos_offset = 3;
break;
case 8:
sample_pos_offset = 7;
break;
case 16:
sample_pos_offset = 15;
break;
default:
break;
}
return sample_pos_offset;
}
static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
LLVMValueRef sample_id)
{
@@ -1638,7 +1653,12 @@ static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
ac_array_in_const_addr_space(ctx->ac.v2f32), "");
sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
uint32_t sample_pos_offset =
radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
sample_id =
LLVMBuildAdd(ctx->ac.builder, sample_id,
LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
return result;

29
src/amd/vulkan/radv_pipeline.c
View File

@@ -2710,35 +2710,6 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *cs,
radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
uint32_t offset;
struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
if (loc->sgpr_idx == -1)
return;
assert(loc->num_sgprs == 1);
assert(!loc->indirect);
switch (pipeline->graphics.ms.num_samples) {
default:
offset = 0;
break;
case 2:
offset = 1;
break;
case 4:
offset = 3;
break;
case 8:
offset = 7;
break;
case 16:
offset = 15;
break;
}
radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
}
}
static void

1
src/amd/vulkan/radv_shader.h
View File

@@ -135,7 +135,6 @@ enum radv_ud_index {
AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
AC_UD_VS_BASE_VERTEX_START_INSTANCE,
AC_UD_VS_MAX_UD,
AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
AC_UD_PS_MAX_UD,
AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
AC_UD_CS_MAX_UD,