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radeonsi: clarify documentation of existing SI workaround

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Limiting LS-HS to a single wave is required on all SI chips due to an
issue with a power management feature.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle
2017-05-03 11:34:33 +02:00
parent f16b755863
commit 707df19451
1 changed files with 3 additions and 1 deletions
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4
src/gallium/drivers/radeonsi/si_state_draw.c
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@@ -184,8 +184,10 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
*/
*num_patches = MIN2(*num_patches, 40);
/* SI bug workaround - limit LS-HS threadgroups to only one wave. */
if (sctx->b.chip_class == SI) {
/* SI bug workaround, related to power management. Limit LS-HS
* threadgroups to only one wave.
*/
unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
*num_patches = MIN2(*num_patches, one_wave);