OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

i965: Upload binding table pointers on Ivybridge.

Browse Source 
Ivybridge uses per-stage commands to update binding table pointers.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke
2011-02-22 13:30:34 -08:00
parent e0e2c04596
commit 706dbf85f1
4 changed files with 16 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/mesa/drivers/dri/i965/brw_defines.h
View File

@@ -832,6 +832,10 @@
# define GEN6_BINDING_TABLE_MODIFY_GS (1 << 9)
# define GEN6_BINDING_TABLE_MODIFY_PS (1 << 12)
#define _3DSTATE_BINDING_TABLE_POINTERS_VS 0x7826 /* GEN7+ */
#define _3DSTATE_BINDING_TABLE_POINTERS_GS 0x7829 /* GEN7+ */
#define _3DSTATE_BINDING_TABLE_POINTERS_PS 0x782A /* GEN7+ */
#define _3DSTATE_SAMPLER_STATE_POINTERS 0x7802 /* GEN6+ */
# define PS_SAMPLER_STATE_CHANGE (1 << 12)
# define GS_SAMPLER_STATE_CHANGE (1 << 9)

2
src/mesa/drivers/dri/i965/brw_state_upload.c
View File

@@ -220,8 +220,6 @@ const struct brw_tracked_state *gen7_atoms[] =
&gen6_scissor_state,
&gen6_binding_table_pointers,
&brw_depthbuffer,
&brw_polygon_stipple,

6
src/mesa/drivers/dri/i965/gen7_vs_state.c
View File

@@ -35,6 +35,11 @@ upload_vs_state(struct brw_context *brw)
struct intel_context *intel = &brw->intel;
struct gl_context *ctx = &intel->ctx;
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
OUT_BATCH(brw->vs.bind_bo_offset);
ADVANCE_BATCH();
if (brw->vs.push_const_size == 0) {
/* Disable the push constant buffers. */
BEGIN_BATCH(7);
@@ -86,6 +91,7 @@ const struct brw_tracked_state gen7_vs_state = {
BRW_NEW_URB_FENCE |
BRW_NEW_CONTEXT |
BRW_NEW_VERTEX_PROGRAM |
BRW_NEW_VS_BINDING_TABLE |
BRW_NEW_BATCH),
.cache = CACHE_NEW_VS_PROG
},

6
src/mesa/drivers/dri/i965/gen7_wm_state.c
View File

@@ -155,6 +155,11 @@ upload_ps_state(struct brw_context *brw)
struct intel_context *intel = &brw->intel;
uint32_t dw2, dw4, dw5;
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
OUT_BATCH(brw->wm.bind_bo_offset);
ADVANCE_BATCH();
/* CACHE_NEW_WM_PROG */
if (brw->wm.prog_data->nr_params == 0) {
/* Disable the push constant buffers. */
@@ -234,6 +239,7 @@ const struct brw_tracked_state gen7_ps_state = {
.brw = (BRW_NEW_CURBE_OFFSETS |
BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_NR_WM_SURFACES |
BRW_NEW_PS_BINDING_TABLE |
BRW_NEW_URB_FENCE |
BRW_NEW_BATCH),
.cache = (CACHE_NEW_SAMPLER |