From 705840d417c8c3a971d81b09de1d1b594ef49f7e Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Tue, 1 Aug 2023 12:18:53 +0300 Subject: [PATCH] anv: get rid of genX(emit_multisample) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The initialization can be simplified and the real programming moved over to genX_pipeline.c Signed-off-by: Lionel Landwerlin Reviewed-by: Tapani Pälli Part-of: --- src/intel/vulkan/anv_genX.h | 2 -- src/intel/vulkan/genX_pipeline.c | 13 +++++++++++-- src/intel/vulkan/genX_state.c | 19 +------------------ 3 files changed, 12 insertions(+), 22 deletions(-) diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h index 345920ebbd3..4964f64140a 100644 --- a/src/intel/vulkan/anv_genX.h +++ b/src/intel/vulkan/anv_genX.h @@ -152,8 +152,6 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch, const unsigned entry_size[4], enum intel_urb_deref_block_size *deref_block_size); -void genX(emit_multisample)(struct anv_batch *batch, uint32_t samples); - void genX(emit_sample_pattern)(struct anv_batch *batch, const struct vk_sample_locations_state *sl); diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index d5c404526c3..1828d5b91e2 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -804,9 +804,18 @@ emit_ms_state(struct anv_graphics_pipeline *pipeline, const struct vk_multisample_state *ms) { struct anv_batch *batch = &pipeline->base.base.batch; + anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) { + ms.NumberofMultisamples = __builtin_ffs(pipeline->rasterization_samples) - 1; - /* On Gfx8+ 3DSTATE_MULTISAMPLE only holds the number of samples. */ - genX(emit_multisample)(batch, pipeline->rasterization_samples); + ms.PixelLocation = CENTER; + + /* The PRM says that this bit is valid only for DX9: + * + * SW can choose to set this bit only for DX9 API. DX10/OGL API's + * should not have any effect by setting or not setting this bit. + */ + ms.PixelPositionOffsetEnable = false; + } } const uint32_t genX(vk_to_intel_logic_op)[] = { diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 2dbc403f90d..b467961f872 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -405,7 +405,7 @@ init_render_queue_state(struct anv_queue *queue) * * Emit this before 3DSTATE_WM_HZ_OP below. */ - genX(emit_multisample)(&batch, 1); + anv_batch_emit(&batch, GENX(3DSTATE_MULTISAMPLE), ms); /* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the * section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer @@ -816,23 +816,6 @@ genX(emit_l3_config)(struct anv_batch *batch, } } -void -genX(emit_multisample)(struct anv_batch *batch, uint32_t samples) -{ - anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) { - ms.NumberofMultisamples = __builtin_ffs(samples) - 1; - - ms.PixelLocation = CENTER; - - /* The PRM says that this bit is valid only for DX9: - * - * SW can choose to set this bit only for DX9 API. DX10/OGL API's - * should not have any effect by setting or not setting this bit. - */ - ms.PixelPositionOffsetEnable = false; - } -} - void genX(emit_sample_pattern)(struct anv_batch *batch, const struct vk_sample_locations_state *sl)