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anv: get rid of genX(emit_multisample)

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The initialization can be simplified and the real programming moved
over to genX_pipeline.c

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
This commit is contained in:
Lionel Landwerlin
2023-08-01 12:18:53 +03:00
committed by Marge Bot
parent eef54f3175
commit 705840d417
3 changed files with 12 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/intel/vulkan/anv_genX.h
View File

@@ -152,8 +152,6 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
const unsigned entry_size[4],
enum intel_urb_deref_block_size *deref_block_size);
void genX(emit_multisample)(struct anv_batch *batch, uint32_t samples);
void genX(emit_sample_pattern)(struct anv_batch *batch,
const struct vk_sample_locations_state *sl);

13
src/intel/vulkan/genX_pipeline.c
View File

@@ -804,9 +804,18 @@ emit_ms_state(struct anv_graphics_pipeline *pipeline,
const struct vk_multisample_state *ms)
{
struct anv_batch *batch = &pipeline->base.base.batch;
anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
ms.NumberofMultisamples = __builtin_ffs(pipeline->rasterization_samples) - 1;
/* On Gfx8+ 3DSTATE_MULTISAMPLE only holds the number of samples. */
genX(emit_multisample)(batch, pipeline->rasterization_samples);
ms.PixelLocation = CENTER;
/* The PRM says that this bit is valid only for DX9:
*
* SW can choose to set this bit only for DX9 API. DX10/OGL API's
* should not have any effect by setting or not setting this bit.
*/
ms.PixelPositionOffsetEnable = false;
}
}
const uint32_t genX(vk_to_intel_logic_op)[] = {

19
src/intel/vulkan/genX_state.c
View File

@@ -405,7 +405,7 @@ init_render_queue_state(struct anv_queue *queue)
*
* Emit this before 3DSTATE_WM_HZ_OP below.
*/
genX(emit_multisample)(&batch, 1);
anv_batch_emit(&batch, GENX(3DSTATE_MULTISAMPLE), ms);
/* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
* section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
@@ -816,23 +816,6 @@ genX(emit_l3_config)(struct anv_batch *batch,
}
}
void
genX(emit_multisample)(struct anv_batch *batch, uint32_t samples)
{
anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
ms.NumberofMultisamples = __builtin_ffs(samples) - 1;
ms.PixelLocation = CENTER;
/* The PRM says that this bit is valid only for DX9:
*
* SW can choose to set this bit only for DX9 API. DX10/OGL API's
* should not have any effect by setting or not setting this bit.
*/
ms.PixelPositionOffsetEnable = false;
}
}
void
genX(emit_sample_pattern)(struct anv_batch *batch,
const struct vk_sample_locations_state *sl)