i965: Move the back-end compiler to src/intel/compiler
Mostly a dummy git mv with a couple of noticable parts: - With the earlier header cleanups, nothing in src/intel depends files from src/mesa/drivers/dri/i965/ - Both Autoconf and Android builds are addressed. Thanks to Mauro and Tapani for the fixups in the latter - brw_util.[ch] is not really compiler specific, so it's moved to i965. v2: - move brw_eu_defines.h instead of brw_defines.h - remove no-longer applicable includes - add missing vulkan/ prefix in the Android build (thanks Tapani) v3: - don't list brw_defines.h in src/intel/Makefile.sources (Jason) - rebase on top of the oa patches [Emil Velikov: commit message, various small fixes througout] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
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Jason Ekstrand
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Emil Velikov
Emil Velikov
parent
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commit
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169
src/intel/compiler/brw_wm_iz.cpp
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169
src/intel/compiler/brw_wm_iz.cpp
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/*
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Copyright (C) Intel Corp. 2006. All Rights Reserved.
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Intel funded Tungsten Graphics to
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develop this 3D driver.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**********************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keithw@vmware.com>
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*/
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#include "brw_fs.h"
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#undef P /* prompted depth */
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#undef C /* computed */
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#undef N /* non-promoted? */
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#define P 0
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#define C 1
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#define N 2
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static const struct {
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GLuint mode:2;
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GLuint sd_present:1;
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GLuint sd_to_rt:1;
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GLuint dd_present:1;
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GLuint ds_present:1;
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} wm_iz_table[BRW_WM_IZ_BIT_MAX] =
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{
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ N, 1, 1, 0, 0 },
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{ N, 0, 1, 0, 0 },
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{ N, 0, 1, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ C, 0, 1, 1, 0 },
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{ C, 0, 1, 1, 0 },
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{ P, 0, 0, 0, 0 },
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{ N, 1, 1, 0, 0 },
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{ C, 0, 1, 1, 0 },
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{ C, 0, 1, 1, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ N, 1, 1, 0, 0 },
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{ N, 0, 1, 0, 0 },
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{ N, 0, 1, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ C, 0, 1, 1, 0 },
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{ C, 0, 1, 1, 0 },
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{ P, 0, 0, 0, 0 },
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{ N, 1, 1, 0, 0 },
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{ C, 0, 1, 1, 0 },
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{ C, 0, 1, 1, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ N, 1, 1, 0, 1 },
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{ N, 0, 1, 0, 1 },
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{ N, 0, 1, 0, 1 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ C, 0, 1, 1, 1 },
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{ C, 0, 1, 1, 1 },
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{ P, 0, 0, 0, 0 },
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{ N, 1, 1, 0, 1 },
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{ C, 0, 1, 1, 1 },
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{ C, 0, 1, 1, 1 },
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{ P, 0, 0, 0, 0 },
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{ C, 0, 0, 0, 1 },
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{ P, 0, 0, 0, 0 },
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{ C, 0, 1, 0, 1 },
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{ P, 0, 0, 0, 0 },
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{ C, 1, 1, 0, 1 },
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{ C, 0, 1, 0, 1 },
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{ C, 0, 1, 0, 1 },
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{ P, 0, 0, 0, 0 },
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{ C, 1, 1, 1, 1 },
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{ C, 0, 1, 1, 1 },
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{ C, 0, 1, 1, 1 },
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{ P, 0, 0, 0, 0 },
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{ C, 1, 1, 1, 1 },
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{ C, 0, 1, 1, 1 },
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{ C, 0, 1, 1, 1 }
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};
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/**
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* \param line_aa BRW_WM_AA_NEVER, BRW_WM_AA_ALWAYS or BRW_WM_AA_SOMETIMES
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* \param lookup bitmask of BRW_WM_IZ_* flags
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*/
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void fs_visitor::setup_fs_payload_gen4()
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{
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assert(stage == MESA_SHADER_FRAGMENT);
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struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
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brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
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GLuint reg = 2;
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bool kill_stats_promoted_workaround = false;
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int lookup = key->iz_lookup;
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assert(lookup < BRW_WM_IZ_BIT_MAX);
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/* Crazy workaround in the windowizer, which we need to track in
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* our register allocation and render target writes. See the "If
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* statistics are enabled..." paragraph of 11.5.3.2: Early Depth
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* Test Cases [Pre-DevGT] of the 3D Pipeline - Windower B-Spec.
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*/
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if (key->stats_wm &&
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(lookup & BRW_WM_IZ_PS_KILL_ALPHATEST_BIT) &&
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wm_iz_table[lookup].mode == P) {
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kill_stats_promoted_workaround = true;
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}
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prog_data->uses_src_depth =
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(nir->info->inputs_read & (1 << VARYING_SLOT_POS)) != 0;
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if (wm_iz_table[lookup].sd_present || prog_data->uses_src_depth ||
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kill_stats_promoted_workaround) {
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payload.source_depth_reg = reg;
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reg += 2;
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}
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if (wm_iz_table[lookup].sd_to_rt || kill_stats_promoted_workaround)
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source_depth_to_render_target = true;
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if (wm_iz_table[lookup].ds_present || key->line_aa != BRW_WM_AA_NEVER) {
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payload.aa_dest_stencil_reg = reg;
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runtime_check_aads_emit =
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!wm_iz_table[lookup].ds_present && key->line_aa == BRW_WM_AA_SOMETIMES;
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reg++;
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}
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if (wm_iz_table[lookup].dd_present) {
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payload.dest_depth_reg = reg;
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reg+=2;
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}
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payload.num_regs = reg;
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}
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