i965: Move the back-end compiler to src/intel/compiler
Mostly a dummy git mv with a couple of noticable parts: - With the earlier header cleanups, nothing in src/intel depends files from src/mesa/drivers/dri/i965/ - Both Autoconf and Android builds are addressed. Thanks to Mauro and Tapani for the fixups in the latter - brw_util.[ch] is not really compiler specific, so it's moved to i965. v2: - move brw_eu_defines.h instead of brw_defines.h - remove no-longer applicable includes - add missing vulkan/ prefix in the Android build (thanks Tapani) v3: - don't list brw_defines.h in src/intel/Makefile.sources (Jason) - rebase on top of the oa patches [Emil Velikov: commit message, various small fixes througout] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Jason Ekstrand
committed by
Emil Velikov
Emil Velikov
parent
d0d4a5f43b
commit
700bebb958
634
src/intel/compiler/brw_vec4_builder.h
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634
src/intel/compiler/brw_vec4_builder.h
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@@ -0,0 +1,634 @@
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/* -*- c++ -*- */
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/*
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* Copyright © 2010-2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
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*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef BRW_VEC4_BUILDER_H
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#define BRW_VEC4_BUILDER_H
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#include "brw_ir_vec4.h"
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#include "brw_ir_allocator.h"
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namespace brw {
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/**
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* Toolbox to assemble a VEC4 IR program out of individual instructions.
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*
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* This object is meant to have an interface consistent with
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* brw::fs_builder. They cannot be fully interchangeable because
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* brw::fs_builder generates scalar code while brw::vec4_builder generates
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* vector code.
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*/
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class vec4_builder {
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public:
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/** Type used in this IR to represent a source of an instruction. */
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typedef brw::src_reg src_reg;
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/** Type used in this IR to represent the destination of an instruction. */
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typedef brw::dst_reg dst_reg;
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/** Type used in this IR to represent an instruction. */
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typedef vec4_instruction instruction;
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/**
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* Construct a vec4_builder that inserts instructions into \p shader.
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*/
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vec4_builder(backend_shader *shader, unsigned dispatch_width = 8) :
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shader(shader), block(NULL), cursor(NULL),
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_dispatch_width(dispatch_width), _group(0),
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force_writemask_all(false),
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annotation()
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{
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}
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/**
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* Construct a vec4_builder that inserts instructions into \p shader
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* before instruction \p inst in basic block \p block. The default
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* execution controls and debug annotation are initialized from the
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* instruction passed as argument.
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*/
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vec4_builder(backend_shader *shader, bblock_t *block, instruction *inst) :
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shader(shader), block(block), cursor(inst),
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_dispatch_width(inst->exec_size), _group(inst->group),
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force_writemask_all(inst->force_writemask_all)
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{
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annotation.str = inst->annotation;
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annotation.ir = inst->ir;
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}
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/**
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* Construct a vec4_builder that inserts instructions before \p cursor
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* in basic block \p block, inheriting other code generation parameters
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* from this.
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*/
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vec4_builder
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at(bblock_t *block, exec_node *cursor) const
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{
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vec4_builder bld = *this;
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bld.block = block;
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bld.cursor = cursor;
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return bld;
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}
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/**
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* Construct a vec4_builder appending instructions at the end of the
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* instruction list of the shader, inheriting other code generation
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* parameters from this.
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*/
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vec4_builder
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at_end() const
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{
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return at(NULL, (exec_node *)&shader->instructions.tail_sentinel);
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}
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/**
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* Construct a builder specifying the default SIMD width and group of
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* channel enable signals, inheriting other code generation parameters
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* from this.
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*
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* \p n gives the default SIMD width, \p i gives the slot group used for
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* predication and control flow masking in multiples of \p n channels.
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*/
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vec4_builder
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group(unsigned n, unsigned i) const
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{
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assert(force_writemask_all ||
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(n <= dispatch_width() && i < dispatch_width() / n));
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vec4_builder bld = *this;
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bld._dispatch_width = n;
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bld._group += i * n;
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return bld;
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}
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/**
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* Construct a builder with per-channel control flow execution masking
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* disabled if \p b is true. If control flow execution masking is
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* already disabled this has no effect.
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*/
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vec4_builder
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exec_all(bool b = true) const
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{
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vec4_builder bld = *this;
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if (b)
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bld.force_writemask_all = true;
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return bld;
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}
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/**
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* Construct a builder with the given debug annotation info.
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*/
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vec4_builder
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annotate(const char *str, const void *ir = NULL) const
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{
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vec4_builder bld = *this;
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bld.annotation.str = str;
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bld.annotation.ir = ir;
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return bld;
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}
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/**
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* Get the SIMD width in use.
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*/
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unsigned
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dispatch_width() const
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{
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return _dispatch_width;
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}
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/**
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* Get the channel group in use.
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*/
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unsigned
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group() const
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{
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return _group;
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}
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/**
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* Allocate a virtual register of natural vector size (four for this IR)
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* and SIMD width. \p n gives the amount of space to allocate in
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* dispatch_width units (which is just enough space for four logical
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* components in this IR).
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*/
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dst_reg
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vgrf(enum brw_reg_type type, unsigned n = 1) const
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{
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assert(dispatch_width() <= 32);
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if (n > 0)
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return retype(dst_reg(VGRF, shader->alloc.allocate(
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n * DIV_ROUND_UP(type_sz(type), 4))),
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type);
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else
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return retype(null_reg_ud(), type);
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}
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/**
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* Create a null register of floating type.
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*/
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dst_reg
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null_reg_f() const
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{
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return dst_reg(retype(brw_null_vec(dispatch_width()),
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BRW_REGISTER_TYPE_F));
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}
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/**
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* Create a null register of signed integer type.
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*/
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dst_reg
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null_reg_d() const
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{
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return dst_reg(retype(brw_null_vec(dispatch_width()),
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BRW_REGISTER_TYPE_D));
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}
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/**
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* Create a null register of unsigned integer type.
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*/
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dst_reg
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null_reg_ud() const
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{
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return dst_reg(retype(brw_null_vec(dispatch_width()),
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BRW_REGISTER_TYPE_UD));
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}
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/**
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* Insert an instruction into the program.
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*/
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instruction *
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emit(const instruction &inst) const
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{
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return emit(new(shader->mem_ctx) instruction(inst));
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}
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/**
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* Create and insert a nullary control instruction into the program.
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*/
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instruction *
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emit(enum opcode opcode) const
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{
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return emit(instruction(opcode));
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}
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/**
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* Create and insert a nullary instruction into the program.
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*/
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instruction *
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emit(enum opcode opcode, const dst_reg &dst) const
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{
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return emit(instruction(opcode, dst));
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}
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/**
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* Create and insert a unary instruction into the program.
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*/
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instruction *
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emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0) const
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{
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switch (opcode) {
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case SHADER_OPCODE_RCP:
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case SHADER_OPCODE_RSQ:
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case SHADER_OPCODE_SQRT:
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case SHADER_OPCODE_EXP2:
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case SHADER_OPCODE_LOG2:
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case SHADER_OPCODE_SIN:
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case SHADER_OPCODE_COS:
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return fix_math_instruction(
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emit(instruction(opcode, dst,
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fix_math_operand(src0))));
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default:
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return emit(instruction(opcode, dst, src0));
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}
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}
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/**
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* Create and insert a binary instruction into the program.
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*/
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instruction *
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emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
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const src_reg &src1) const
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{
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switch (opcode) {
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case SHADER_OPCODE_POW:
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case SHADER_OPCODE_INT_QUOTIENT:
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case SHADER_OPCODE_INT_REMAINDER:
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return fix_math_instruction(
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emit(instruction(opcode, dst,
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fix_math_operand(src0),
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fix_math_operand(src1))));
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default:
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return emit(instruction(opcode, dst, src0, src1));
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}
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}
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/**
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* Create and insert a ternary instruction into the program.
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*/
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instruction *
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emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
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const src_reg &src1, const src_reg &src2) const
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{
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switch (opcode) {
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case BRW_OPCODE_BFE:
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case BRW_OPCODE_BFI2:
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case BRW_OPCODE_MAD:
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case BRW_OPCODE_LRP:
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return emit(instruction(opcode, dst,
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fix_3src_operand(src0),
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fix_3src_operand(src1),
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fix_3src_operand(src2)));
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default:
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return emit(instruction(opcode, dst, src0, src1, src2));
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}
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}
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/**
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* Insert a preallocated instruction into the program.
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*/
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instruction *
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emit(instruction *inst) const
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{
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inst->exec_size = dispatch_width();
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inst->group = group();
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inst->force_writemask_all = force_writemask_all;
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inst->size_written = inst->exec_size * type_sz(inst->dst.type);
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inst->annotation = annotation.str;
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inst->ir = annotation.ir;
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if (block)
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static_cast<instruction *>(cursor)->insert_before(block, inst);
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else
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cursor->insert_before(inst);
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return inst;
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}
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/**
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* Select \p src0 if the comparison of both sources with the given
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* conditional mod evaluates to true, otherwise select \p src1.
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*
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* Generally useful to get the minimum or maximum of two values.
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*/
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instruction *
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emit_minmax(const dst_reg &dst, const src_reg &src0,
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const src_reg &src1, brw_conditional_mod mod) const
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{
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assert(mod == BRW_CONDITIONAL_GE || mod == BRW_CONDITIONAL_L);
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return set_condmod(mod, SEL(dst, fix_unsigned_negate(src0),
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fix_unsigned_negate(src1)));
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}
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/**
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* Copy any live channel from \p src to the first channel of the result.
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*/
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src_reg
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emit_uniformize(const src_reg &src) const
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{
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const vec4_builder ubld = exec_all();
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const dst_reg chan_index =
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writemask(vgrf(BRW_REGISTER_TYPE_UD), WRITEMASK_X);
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const dst_reg dst = vgrf(src.type);
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ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index);
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ubld.emit(SHADER_OPCODE_BROADCAST, dst, src, src_reg(chan_index));
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return src_reg(dst);
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}
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/**
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* Assorted arithmetic ops.
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* @{
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*/
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#define ALU1(op) \
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instruction * \
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op(const dst_reg &dst, const src_reg &src0) const \
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{ \
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return emit(BRW_OPCODE_##op, dst, src0); \
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}
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#define ALU2(op) \
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instruction * \
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op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) const \
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{ \
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return emit(BRW_OPCODE_##op, dst, src0, src1); \
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}
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#define ALU2_ACC(op) \
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instruction * \
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op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) const \
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{ \
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instruction *inst = emit(BRW_OPCODE_##op, dst, src0, src1); \
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inst->writes_accumulator = true; \
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return inst; \
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}
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#define ALU3(op) \
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instruction * \
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op(const dst_reg &dst, const src_reg &src0, const src_reg &src1, \
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const src_reg &src2) const \
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{ \
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return emit(BRW_OPCODE_##op, dst, src0, src1, src2); \
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}
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ALU2(ADD)
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ALU2_ACC(ADDC)
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ALU2(AND)
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ALU2(ASR)
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ALU2(AVG)
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ALU3(BFE)
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ALU2(BFI1)
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ALU3(BFI2)
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ALU1(BFREV)
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ALU1(CBIT)
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ALU2(CMPN)
|
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ALU3(CSEL)
|
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ALU1(DIM)
|
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ALU2(DP2)
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ALU2(DP3)
|
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ALU2(DP4)
|
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ALU2(DPH)
|
||||
ALU1(F16TO32)
|
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ALU1(F32TO16)
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||||
ALU1(FBH)
|
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ALU1(FBL)
|
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ALU1(FRC)
|
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ALU2(LINE)
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||||
ALU1(LZD)
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ALU2(MAC)
|
||||
ALU2_ACC(MACH)
|
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ALU3(MAD)
|
||||
ALU1(MOV)
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||||
ALU2(MUL)
|
||||
ALU1(NOT)
|
||||
ALU2(OR)
|
||||
ALU2(PLN)
|
||||
ALU1(RNDD)
|
||||
ALU1(RNDE)
|
||||
ALU1(RNDU)
|
||||
ALU1(RNDZ)
|
||||
ALU2(SAD2)
|
||||
ALU2_ACC(SADA2)
|
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ALU2(SEL)
|
||||
ALU2(SHL)
|
||||
ALU2(SHR)
|
||||
ALU2_ACC(SUBB)
|
||||
ALU2(XOR)
|
||||
|
||||
#undef ALU3
|
||||
#undef ALU2_ACC
|
||||
#undef ALU2
|
||||
#undef ALU1
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* CMP: Sets the low bit of the destination channels with the result
|
||||
* of the comparison, while the upper bits are undefined, and updates
|
||||
* the flag register with the packed 16 bits of the result.
|
||||
*/
|
||||
instruction *
|
||||
CMP(const dst_reg &dst, const src_reg &src0, const src_reg &src1,
|
||||
brw_conditional_mod condition) const
|
||||
{
|
||||
/* Take the instruction:
|
||||
*
|
||||
* CMP null<d> src0<f> src1<f>
|
||||
*
|
||||
* Original gen4 does type conversion to the destination type
|
||||
* before comparison, producing garbage results for floating
|
||||
* point comparisons.
|
||||
*
|
||||
* The destination type doesn't matter on newer generations,
|
||||
* so we set the type to match src0 so we can compact the
|
||||
* instruction.
|
||||
*/
|
||||
return set_condmod(condition,
|
||||
emit(BRW_OPCODE_CMP, retype(dst, src0.type),
|
||||
fix_unsigned_negate(src0),
|
||||
fix_unsigned_negate(src1)));
|
||||
}
|
||||
|
||||
/**
|
||||
* Gen4 predicated IF.
|
||||
*/
|
||||
instruction *
|
||||
IF(brw_predicate predicate) const
|
||||
{
|
||||
return set_predicate(predicate, emit(BRW_OPCODE_IF));
|
||||
}
|
||||
|
||||
/**
|
||||
* Gen6 IF with embedded comparison.
|
||||
*/
|
||||
instruction *
|
||||
IF(const src_reg &src0, const src_reg &src1,
|
||||
brw_conditional_mod condition) const
|
||||
{
|
||||
assert(shader->devinfo->gen == 6);
|
||||
return set_condmod(condition,
|
||||
emit(BRW_OPCODE_IF,
|
||||
null_reg_d(),
|
||||
fix_unsigned_negate(src0),
|
||||
fix_unsigned_negate(src1)));
|
||||
}
|
||||
|
||||
/**
|
||||
* Emit a linear interpolation instruction.
|
||||
*/
|
||||
instruction *
|
||||
LRP(const dst_reg &dst, const src_reg &x, const src_reg &y,
|
||||
const src_reg &a) const
|
||||
{
|
||||
if (shader->devinfo->gen >= 6) {
|
||||
/* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
|
||||
* we need to reorder the operands.
|
||||
*/
|
||||
return emit(BRW_OPCODE_LRP, dst, a, y, x);
|
||||
|
||||
} else {
|
||||
/* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
|
||||
const dst_reg y_times_a = vgrf(dst.type);
|
||||
const dst_reg one_minus_a = vgrf(dst.type);
|
||||
const dst_reg x_times_one_minus_a = vgrf(dst.type);
|
||||
|
||||
MUL(y_times_a, y, a);
|
||||
ADD(one_minus_a, negate(a), brw_imm_f(1.0f));
|
||||
MUL(x_times_one_minus_a, x, src_reg(one_minus_a));
|
||||
return ADD(dst, src_reg(x_times_one_minus_a), src_reg(y_times_a));
|
||||
}
|
||||
}
|
||||
|
||||
backend_shader *shader;
|
||||
|
||||
protected:
|
||||
/**
|
||||
* Workaround for negation of UD registers. See comment in
|
||||
* fs_generator::generate_code() for the details.
|
||||
*/
|
||||
src_reg
|
||||
fix_unsigned_negate(const src_reg &src) const
|
||||
{
|
||||
if (src.type == BRW_REGISTER_TYPE_UD && src.negate) {
|
||||
dst_reg temp = vgrf(BRW_REGISTER_TYPE_UD);
|
||||
MOV(temp, src);
|
||||
return src_reg(temp);
|
||||
} else {
|
||||
return src;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Workaround for register access modes not supported by the ternary
|
||||
* instruction encoding.
|
||||
*/
|
||||
src_reg
|
||||
fix_3src_operand(const src_reg &src) const
|
||||
{
|
||||
/* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
|
||||
* able to use vertical stride of zero to replicate the vec4 uniform, like
|
||||
*
|
||||
* g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
|
||||
*
|
||||
* But you can't, since vertical stride is always four in three-source
|
||||
* instructions. Instead, insert a MOV instruction to do the replication so
|
||||
* that the three-source instruction can consume it.
|
||||
*/
|
||||
|
||||
/* The MOV is only needed if the source is a uniform or immediate. */
|
||||
if (src.file != UNIFORM && src.file != IMM)
|
||||
return src;
|
||||
|
||||
if (src.file == UNIFORM && brw_is_single_value_swizzle(src.swizzle))
|
||||
return src;
|
||||
|
||||
const dst_reg expanded = vgrf(src.type);
|
||||
emit(VEC4_OPCODE_UNPACK_UNIFORM, expanded, src);
|
||||
return src_reg(expanded);
|
||||
}
|
||||
|
||||
/**
|
||||
* Workaround for register access modes not supported by the math
|
||||
* instruction.
|
||||
*/
|
||||
src_reg
|
||||
fix_math_operand(const src_reg &src) const
|
||||
{
|
||||
/* The gen6 math instruction ignores the source modifiers --
|
||||
* swizzle, abs, negate, and at least some parts of the register
|
||||
* region description.
|
||||
*
|
||||
* Rather than trying to enumerate all these cases, *always* expand the
|
||||
* operand to a temp GRF for gen6.
|
||||
*
|
||||
* For gen7, keep the operand as-is, except if immediate, which gen7 still
|
||||
* can't use.
|
||||
*/
|
||||
if (shader->devinfo->gen == 6 ||
|
||||
(shader->devinfo->gen == 7 && src.file == IMM)) {
|
||||
const dst_reg tmp = vgrf(src.type);
|
||||
MOV(tmp, src);
|
||||
return src_reg(tmp);
|
||||
} else {
|
||||
return src;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Workaround other weirdness of the math instruction.
|
||||
*/
|
||||
instruction *
|
||||
fix_math_instruction(instruction *inst) const
|
||||
{
|
||||
if (shader->devinfo->gen == 6 &&
|
||||
inst->dst.writemask != WRITEMASK_XYZW) {
|
||||
const dst_reg tmp = vgrf(inst->dst.type);
|
||||
MOV(inst->dst, src_reg(tmp));
|
||||
inst->dst = tmp;
|
||||
|
||||
} else if (shader->devinfo->gen < 6) {
|
||||
const unsigned sources = (inst->src[1].file == BAD_FILE ? 1 : 2);
|
||||
inst->base_mrf = 1;
|
||||
inst->mlen = sources;
|
||||
}
|
||||
|
||||
return inst;
|
||||
}
|
||||
|
||||
bblock_t *block;
|
||||
exec_node *cursor;
|
||||
|
||||
unsigned _dispatch_width;
|
||||
unsigned _group;
|
||||
bool force_writemask_all;
|
||||
|
||||
/** Debug annotation info. */
|
||||
struct {
|
||||
const char *str;
|
||||
const void *ir;
|
||||
} annotation;
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user