i965: Move the back-end compiler to src/intel/compiler
Mostly a dummy git mv with a couple of noticable parts: - With the earlier header cleanups, nothing in src/intel depends files from src/mesa/drivers/dri/i965/ - Both Autoconf and Android builds are addressed. Thanks to Mauro and Tapani for the fixups in the latter - brw_util.[ch] is not really compiler specific, so it's moved to i965. v2: - move brw_eu_defines.h instead of brw_defines.h - remove no-longer applicable includes - add missing vulkan/ prefix in the Android build (thanks Tapani) v3: - don't list brw_defines.h in src/intel/Makefile.sources (Jason) - rebase on top of the oa patches [Emil Velikov: commit message, various small fixes througout] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Jason Ekstrand
committed by
Emil Velikov
Emil Velikov
parent
d0d4a5f43b
commit
700bebb958
220
src/intel/compiler/brw_fs_sel_peephole.cpp
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src/intel/compiler/brw_fs_sel_peephole.cpp
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/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_fs.h"
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#include "brw_cfg.h"
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/** @file brw_fs_sel_peephole.cpp
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*
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* This file contains the opt_peephole_sel() optimization pass that replaces
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* MOV instructions to the same destination in the "then" and "else" bodies of
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* an if statement with SEL instructions.
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*/
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/* Four MOVs seems to be pretty typical, so I picked the next power of two in
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* the hopes that it would handle almost anything possible in a single
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* pass.
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*/
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#define MAX_MOVS 8 /**< The maximum number of MOVs to attempt to match. */
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using namespace brw;
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/**
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* Scans forwards from an IF counting consecutive MOV instructions in the
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* "then" and "else" blocks of the if statement.
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*
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* A pointer to the bblock_t following the IF is passed as the <then_block>
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* argument. The function stores pointers to the MOV instructions in the
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* <then_mov> and <else_mov> arrays.
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*
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* \return the minimum number of MOVs found in the two branches or zero if
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* an error occurred.
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*
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* E.g.:
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* IF ...
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* then_mov[0] = MOV g4, ...
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* then_mov[1] = MOV g5, ...
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* then_mov[2] = MOV g6, ...
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* ELSE ...
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* else_mov[0] = MOV g4, ...
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* else_mov[1] = MOV g5, ...
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* else_mov[2] = MOV g7, ...
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* ENDIF
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* returns 3.
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*/
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static int
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count_movs_from_if(fs_inst *then_mov[MAX_MOVS], fs_inst *else_mov[MAX_MOVS],
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bblock_t *then_block, bblock_t *else_block)
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{
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int then_movs = 0;
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foreach_inst_in_block(fs_inst, inst, then_block) {
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if (then_movs == MAX_MOVS || inst->opcode != BRW_OPCODE_MOV)
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break;
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then_mov[then_movs] = inst;
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then_movs++;
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}
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int else_movs = 0;
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foreach_inst_in_block(fs_inst, inst, else_block) {
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if (else_movs == MAX_MOVS || inst->opcode != BRW_OPCODE_MOV)
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break;
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else_mov[else_movs] = inst;
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else_movs++;
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}
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return MIN2(then_movs, else_movs);
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}
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/**
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* Try to replace IF/MOV+/ELSE/MOV+/ENDIF with SEL.
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*
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* Many GLSL shaders contain the following pattern:
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*
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* x = condition ? foo : bar
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*
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* or
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*
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* if (...) a.xyzw = foo.xyzw;
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* else a.xyzw = bar.xyzw;
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*
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* The compiler emits an ir_if tree for this, since each subexpression might be
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* a complex tree that could have side-effects or short-circuit logic.
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*
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* However, the common case is to simply select one of two constants or
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* variable values---which is exactly what SEL is for. In this case, the
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* assembly looks like:
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*
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* (+f0) IF
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* MOV dst src0
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* ...
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* ELSE
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* MOV dst src1
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* ...
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* ENDIF
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*
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* where each pair of MOVs to a common destination and can be easily translated
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* into
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*
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* (+f0) SEL dst src0 src1
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*
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* If src0 is an immediate value, we promote it to a temporary GRF.
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*/
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bool
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fs_visitor::opt_peephole_sel()
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{
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bool progress = false;
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foreach_block (block, cfg) {
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/* IF instructions, by definition, can only be found at the ends of
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* basic blocks.
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*/
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fs_inst *if_inst = (fs_inst *)block->end();
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if (if_inst->opcode != BRW_OPCODE_IF)
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continue;
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fs_inst *else_mov[MAX_MOVS] = { NULL };
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fs_inst *then_mov[MAX_MOVS] = { NULL };
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bblock_t *then_block = block->next();
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bblock_t *else_block = NULL;
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foreach_list_typed(bblock_link, child, link, &block->children) {
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if (child->block != then_block) {
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if (child->block->prev()->end()->opcode == BRW_OPCODE_ELSE) {
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else_block = child->block;
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}
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break;
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}
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}
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if (else_block == NULL)
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continue;
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int movs = count_movs_from_if(then_mov, else_mov, then_block, else_block);
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if (movs == 0)
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continue;
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/* Generate SEL instructions for pairs of MOVs to a common destination. */
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for (int i = 0; i < movs; i++) {
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if (!then_mov[i] || !else_mov[i])
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break;
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/* Check that the MOVs are the right form. */
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if (!then_mov[i]->dst.equals(else_mov[i]->dst) ||
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then_mov[i]->exec_size != else_mov[i]->exec_size ||
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then_mov[i]->group != else_mov[i]->group ||
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then_mov[i]->force_writemask_all != else_mov[i]->force_writemask_all ||
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then_mov[i]->is_partial_write() ||
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else_mov[i]->is_partial_write() ||
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then_mov[i]->conditional_mod != BRW_CONDITIONAL_NONE ||
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else_mov[i]->conditional_mod != BRW_CONDITIONAL_NONE) {
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movs = i;
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break;
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}
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/* Check that source types for mov operations match. */
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if (then_mov[i]->src[0].type != else_mov[i]->src[0].type) {
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movs = i;
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break;
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}
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}
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if (movs == 0)
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continue;
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for (int i = 0; i < movs; i++) {
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const fs_builder ibld = fs_builder(this, then_block, then_mov[i])
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.at(block, if_inst);
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if (then_mov[i]->src[0].equals(else_mov[i]->src[0])) {
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ibld.MOV(then_mov[i]->dst, then_mov[i]->src[0]);
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} else {
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/* Only the last source register can be a constant, so if the MOV
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* in the "then" clause uses a constant, we need to put it in a
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* temporary.
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*/
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fs_reg src0(then_mov[i]->src[0]);
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if (src0.file == IMM) {
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src0 = vgrf(glsl_type::float_type);
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src0.type = then_mov[i]->src[0].type;
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ibld.MOV(src0, then_mov[i]->src[0]);
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}
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set_predicate_inv(if_inst->predicate, if_inst->predicate_inverse,
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ibld.SEL(then_mov[i]->dst, src0,
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else_mov[i]->src[0]));
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}
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then_mov[i]->remove(then_block);
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else_mov[i]->remove(else_block);
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}
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progress = true;
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}
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if (progress)
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invalidate_live_intervals();
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return progress;
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}
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