i965: Move the back-end compiler to src/intel/compiler
Mostly a dummy git mv with a couple of noticable parts: - With the earlier header cleanups, nothing in src/intel depends files from src/mesa/drivers/dri/i965/ - Both Autoconf and Android builds are addressed. Thanks to Mauro and Tapani for the fixups in the latter - brw_util.[ch] is not really compiler specific, so it's moved to i965. v2: - move brw_eu_defines.h instead of brw_defines.h - remove no-longer applicable includes - add missing vulkan/ prefix in the Android build (thanks Tapani) v3: - don't list brw_defines.h in src/intel/Makefile.sources (Jason) - rebase on top of the oa patches [Emil Velikov: commit message, various small fixes througout] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
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Jason Ekstrand
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Emil Velikov
Emil Velikov
parent
d0d4a5f43b
commit
700bebb958
160
src/intel/compiler/brw_compiler.c
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160
src/intel/compiler/brw_compiler.c
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/*
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* Copyright © 2015-2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_compiler.h"
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#include "brw_shader.h"
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#include "brw_eu.h"
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#include "common/gen_debug.h"
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#include "compiler/nir/nir.h"
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#include "main/errors.h"
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#include "util/debug.h"
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#define COMMON_OPTIONS \
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.lower_sub = true, \
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.lower_fdiv = true, \
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.lower_scmp = true, \
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.lower_fmod32 = true, \
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.lower_fmod64 = false, \
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.lower_bitfield_extract = true, \
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.lower_bitfield_insert = true, \
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.lower_uadd_carry = true, \
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.lower_usub_borrow = true, \
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.lower_fdiv = true, \
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.lower_flrp64 = true, \
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.native_integers = true, \
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.use_interpolated_input_intrinsics = true, \
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.vertex_id_zero_based = true
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static const struct nir_shader_compiler_options scalar_nir_options = {
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COMMON_OPTIONS,
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.lower_pack_half_2x16 = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_snorm_4x8 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_pack_unorm_4x8 = true,
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.lower_unpack_half_2x16 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_snorm_4x8 = true,
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.lower_unpack_unorm_2x16 = true,
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.lower_unpack_unorm_4x8 = true,
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.max_unroll_iterations = 32,
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};
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static const struct nir_shader_compiler_options vector_nir_options = {
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COMMON_OPTIONS,
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/* In the vec4 backend, our dpN instruction replicates its result to all the
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* components of a vec4. We would like NIR to give us replicated fdot
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* instructions because it can optimize better for us.
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*/
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.fdot_replicates = true,
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/* Prior to Gen6, there are no three source operations for SIMD4x2. */
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.lower_flrp32 = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_unorm_2x16 = true,
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.lower_extract_byte = true,
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.lower_extract_word = true,
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.max_unroll_iterations = 32,
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};
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static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
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COMMON_OPTIONS,
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/* In the vec4 backend, our dpN instruction replicates its result to all the
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* components of a vec4. We would like NIR to give us replicated fdot
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* instructions because it can optimize better for us.
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*/
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.fdot_replicates = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_unorm_2x16 = true,
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.lower_extract_byte = true,
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.lower_extract_word = true,
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.max_unroll_iterations = 32,
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};
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struct brw_compiler *
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brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
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{
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struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
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compiler->devinfo = devinfo;
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brw_fs_alloc_reg_sets(compiler);
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brw_vec4_alloc_reg_set(compiler);
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brw_init_compaction_tables(devinfo);
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compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
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compiler->scalar_stage[MESA_SHADER_VERTEX] =
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devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
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compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
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devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
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compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
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devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
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compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
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devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
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compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
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compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
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/* We want the GLSL compiler to emit code that uses condition codes */
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for (int i = 0; i < MESA_SHADER_STAGES; i++) {
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compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
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compiler->glsl_compiler_options[i].MaxIfDepth =
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devinfo->gen < 6 ? 16 : UINT_MAX;
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compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
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compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
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bool is_scalar = compiler->scalar_stage[i];
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compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
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compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
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compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
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if (is_scalar) {
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compiler->glsl_compiler_options[i].NirOptions = &scalar_nir_options;
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} else {
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compiler->glsl_compiler_options[i].NirOptions =
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devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
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}
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compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
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compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
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}
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compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
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compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
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compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
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if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
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compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
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return compiler;
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}
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