agx: Model both sources of sample_mask
We need to control both sources to implement multisampling properly. The semantic is something like: foreach sample in the first mask { if correspond bit in second bit set { make sample live } else { make sample dead } } But I'm reticent to document more formally until the details are really understood and properly tested. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23480>
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@@ -428,7 +428,7 @@ agx_write_sample_mask_1(agx_builder *b)
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* we are therefore still active and need to write a full sample mask.
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* we are therefore still active and need to write a full sample mask.
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* TODO: interactions with MSAA and gl_SampleMask writes
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* TODO: interactions with MSAA and gl_SampleMask writes
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*/
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*/
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agx_sample_mask(b, agx_immediate(1));
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agx_sample_mask(b, agx_immediate(0xFF), agx_immediate(1));
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agx_signal_pix(b, 1);
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agx_signal_pix(b, 1);
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b->shader->did_sample_mask = true;
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b->shader->did_sample_mask = true;
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@@ -688,7 +688,7 @@ agx_emit_discard(agx_builder *b)
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b->shader->did_writeout = true;
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b->shader->did_writeout = true;
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b->shader->out->writes_sample_mask = true;
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b->shader->out->writes_sample_mask = true;
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agx_sample_mask(b, agx_immediate(0));
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agx_sample_mask(b, agx_immediate(0xFF), agx_immediate(0));
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return agx_signal_pix(b, 1);
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return agx_signal_pix(b, 1);
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}
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}
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@@ -41,6 +41,7 @@ should_lower(enum agx_opcode op, agx_index uniform, unsigned src_index)
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case AGX_OPCODE_UNIFORM_STORE:
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case AGX_OPCODE_UNIFORM_STORE:
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case AGX_OPCODE_ST_VARY:
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case AGX_OPCODE_ST_VARY:
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case AGX_OPCODE_LOCAL_ATOMIC:
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case AGX_OPCODE_LOCAL_ATOMIC:
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case AGX_OPCODE_SAMPLE_MASK:
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return true;
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return true;
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default:
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default:
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return false;
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return false;
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@@ -292,7 +292,7 @@ op("wait", (0x38, 0xFF, 2, _), dests = 0,
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op("get_sr", (0x72, 0x7F | L, 4, _), dests = 1, imms = [SR])
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op("get_sr", (0x72, 0x7F | L, 4, _), dests = 1, imms = [SR])
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op("sample_mask", (0x7fc1, 0xffff, 6, _), dests = 0, srcs = 1, can_eliminate = False)
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op("sample_mask", (0x7fc1, 0xffff, 6, _), dests = 0, srcs = 2, can_eliminate = False)
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# Sources: sample mask, combined depth/stencil
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# Sources: sample mask, combined depth/stencil
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op("zs_emit", (0x41, 0xFF | L, 4, _), dests = 0, srcs = 2,
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op("zs_emit", (0x41, 0xFF | L, 4, _), dests = 0, srcs = 2,
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@@ -502,9 +502,10 @@ agx_pack_instr(struct util_dynarray *emission, struct util_dynarray *fixups,
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}
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}
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case AGX_OPCODE_SAMPLE_MASK: {
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case AGX_OPCODE_SAMPLE_MASK: {
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unsigned S = agx_pack_sample_mask_src(I->src[0]);
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unsigned S = agx_pack_sample_mask_src(I->src[1]);
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unsigned T = 0xFF;
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unsigned T = I->src[0].value;
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bool Tt = true /* immediate */;
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bool Tt = I->src[0].type == AGX_INDEX_IMMEDIATE;
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assert(Tt || I->src[0].type == AGX_INDEX_REGISTER);
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uint32_t raw = 0xc1 | (Tt ? BITFIELD_BIT(8) : 0) |
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uint32_t raw = 0xc1 | (Tt ? BITFIELD_BIT(8) : 0) |
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((T & BITFIELD_MASK(6)) << 9) | ((S & 0xff) << 16) |
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((T & BITFIELD_MASK(6)) << 9) | ((S & 0xff) << 16) |
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((T >> 6) << 24) | ((S >> 8) << 26);
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((T >> 6) << 24) | ((S >> 8) << 26);
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