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intel/fs: Track instance id in gs_thread_payload

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This change moves the instance id gs_thread_payload constructor and
lowering code will simply use that.

Also, this change takes the Xe2 register width in consideration that
fixes a couple of tests involving geometry shaders with gl_InvocationID
on Xe2.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26960>
This commit is contained in:
Sagar Ghuge
2024-01-09 13:04:49 -08:00
committed by Marge Bot
parent 0384e96aee
commit 6fcec87090
3 changed files with 7 additions and 5 deletions
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1
src/intel/compiler/brw_fs.h
View File

@@ -122,6 +122,7 @@ struct gs_thread_payload : public thread_payload {
fs_reg urb_handles;
fs_reg primitive_id;
fs_reg instance_id;
fs_reg icp_handle_start;
};

6
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -220,11 +220,7 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block)
assert(s.stage == MESA_SHADER_GEOMETRY);
reg = &ntb.system_values[SYSTEM_VALUE_INVOCATION_ID];
if (reg->file == BAD_FILE) {
const fs_builder abld = ntb.bld.annotate("gl_InvocationID", NULL);
fs_reg g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
fs_reg iid = abld.vgrf(BRW_REGISTER_TYPE_UD, 1);
abld.SHR(iid, g1, brw_imm_ud(27u));
*reg = iid;
*reg = s.gs_payload().instance_id;
}
break;

5
src/intel/compiler/brw_fs_thread_payload.cpp
View File

@@ -113,6 +113,11 @@ gs_thread_payload::gs_thread_payload(fs_visitor &v)
urb_handles = bld.vgrf(BRW_REGISTER_TYPE_UD);
bld.AND(urb_handles, brw_ud8_grf(r, 0),
v.devinfo->ver >= 20 ? brw_imm_ud(0xFFFFFF) : brw_imm_ud(0xFFFF));
/* R1: Instance ID stored in bits 31:27 */
instance_id = bld.vgrf(BRW_REGISTER_TYPE_UD);
bld.SHR(instance_id, brw_ud8_grf(r, 0), brw_imm_ud(27u));
r += reg_unit(v.devinfo);
if (gs_prog_data->include_primitive_id) {