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radv: Add radv_shader_type to fix gs_copy and trap handler handling

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is_gs_copy_shader and is_trap_handler_shader were cleared in
radv_init_shader_args. This restores the original behaviour.

Fixes: 67635bb ("radv: zero-initialize radv_shader_args right before declaring them")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22382>
This commit is contained in:
Konstantin Seurer
2023-04-09 11:26:52 +02:00
committed by Marge Bot
parent c66be7521f
commit 6f9bb453ef
6 changed files with 34 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/amd/vulkan/radv_aco_shader_info.h
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@@ -67,7 +67,7 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info,
ASSIGN_FIELD(cs.subgroup_size); ASSIGN_FIELD(cs.subgroup_size);
ASSIGN_FIELD(cs.uses_full_subgroups); ASSIGN_FIELD(cs.uses_full_subgroups);
aco_info->gfx9_gs_ring_lds_size = radv->gs_ring_info.lds_size; aco_info->gfx9_gs_ring_lds_size = radv->gs_ring_info.lds_size;
aco_info->is_trap_handler_shader = radv_args->is_trap_handler_shader; aco_info->is_trap_handler_shader = radv_args->type == RADV_SHADER_TYPE_TRAP_HANDLER;
} }
#define ASSIGN_VS_STATE_FIELD(x) aco_info->state.x = radv->state->x #define ASSIGN_VS_STATE_FIELD(x) aco_info->state.x = radv->state->x

11
src/amd/vulkan/radv_pipeline.c
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@@ -2364,7 +2364,7 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
if (gfx_level >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) { if (gfx_level >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) {
radv_declare_shader_args(device, pipeline_key, &stages[MESA_SHADER_TESS_CTRL].info, radv_declare_shader_args(device, pipeline_key, &stages[MESA_SHADER_TESS_CTRL].info,
MESA_SHADER_TESS_CTRL, true, MESA_SHADER_VERTEX, MESA_SHADER_TESS_CTRL, true, MESA_SHADER_VERTEX,
&stages[MESA_SHADER_TESS_CTRL].args); RADV_SHADER_TYPE_DEFAULT, &stages[MESA_SHADER_TESS_CTRL].args);
stages[MESA_SHADER_TESS_CTRL].info.user_sgprs_locs = stages[MESA_SHADER_TESS_CTRL].args.user_sgprs_locs; stages[MESA_SHADER_TESS_CTRL].info.user_sgprs_locs = stages[MESA_SHADER_TESS_CTRL].args.user_sgprs_locs;
stages[MESA_SHADER_TESS_CTRL].info.inline_push_constant_mask = stages[MESA_SHADER_TESS_CTRL].info.inline_push_constant_mask =
stages[MESA_SHADER_TESS_CTRL].args.ac.inline_push_const_mask; stages[MESA_SHADER_TESS_CTRL].args.ac.inline_push_const_mask;
@@ -2381,7 +2381,7 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
gl_shader_stage pre_stage = gl_shader_stage pre_stage =
stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
radv_declare_shader_args(device, pipeline_key, &stages[MESA_SHADER_GEOMETRY].info, radv_declare_shader_args(device, pipeline_key, &stages[MESA_SHADER_GEOMETRY].info,
MESA_SHADER_GEOMETRY, true, pre_stage, MESA_SHADER_GEOMETRY, true, pre_stage, RADV_SHADER_TYPE_DEFAULT,
&stages[MESA_SHADER_GEOMETRY].args); &stages[MESA_SHADER_GEOMETRY].args);
stages[MESA_SHADER_GEOMETRY].info.user_sgprs_locs = stages[MESA_SHADER_GEOMETRY].args.user_sgprs_locs; stages[MESA_SHADER_GEOMETRY].info.user_sgprs_locs = stages[MESA_SHADER_GEOMETRY].args.user_sgprs_locs;
stages[MESA_SHADER_GEOMETRY].info.inline_push_constant_mask = stages[MESA_SHADER_GEOMETRY].info.inline_push_constant_mask =
@@ -2396,7 +2396,7 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
u_foreach_bit(i, active_nir_stages) { u_foreach_bit(i, active_nir_stages) {
radv_declare_shader_args(device, pipeline_key, &stages[i].info, i, false, MESA_SHADER_VERTEX, radv_declare_shader_args(device, pipeline_key, &stages[i].info, i, false, MESA_SHADER_VERTEX,
&stages[i].args); RADV_SHADER_TYPE_DEFAULT, &stages[i].args);
stages[i].info.user_sgprs_locs = stages[i].args.user_sgprs_locs; stages[i].info.user_sgprs_locs = stages[i].args.user_sgprs_locs;
stages[i].info.inline_push_constant_mask = stages[i].args.ac.inline_push_const_mask; stages[i].info.inline_push_constant_mask = stages[i].args.ac.inline_push_const_mask;
} }
@@ -2667,9 +2667,8 @@ radv_pipeline_create_gs_copy_shader(struct radv_device *device, struct radv_pipe
gs_copy_stage.info.outinfo = gs_info->outinfo; gs_copy_stage.info.outinfo = gs_info->outinfo;
gs_copy_stage.info.force_vrs_per_vertex = gs_info->force_vrs_per_vertex; gs_copy_stage.info.force_vrs_per_vertex = gs_info->force_vrs_per_vertex;
gs_copy_stage.args.is_gs_copy_shader = true;
radv_declare_shader_args(device, pipeline_key, &gs_copy_stage.info, MESA_SHADER_VERTEX, false, radv_declare_shader_args(device, pipeline_key, &gs_copy_stage.info, MESA_SHADER_VERTEX, false,
MESA_SHADER_VERTEX, &gs_copy_stage.args); MESA_SHADER_VERTEX, RADV_SHADER_TYPE_GS_COPY, &gs_copy_stage.args);
gs_copy_stage.info.user_sgprs_locs = gs_copy_stage.args.user_sgprs_locs; gs_copy_stage.info.user_sgprs_locs = gs_copy_stage.args.user_sgprs_locs;
gs_copy_stage.info.inline_push_constant_mask = gs_copy_stage.args.ac.inline_push_const_mask; gs_copy_stage.info.inline_push_constant_mask = gs_copy_stage.args.ac.inline_push_const_mask;
@@ -5159,7 +5158,7 @@ radv_compute_pipeline_compile(struct radv_compute_pipeline *pipeline,
cs_stage.args.load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr; cs_stage.args.load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr;
radv_declare_shader_args(device, pipeline_key, &cs_stage.info, MESA_SHADER_COMPUTE, false, radv_declare_shader_args(device, pipeline_key, &cs_stage.info, MESA_SHADER_COMPUTE, false,
MESA_SHADER_VERTEX, &cs_stage.args); MESA_SHADER_VERTEX, RADV_SHADER_TYPE_DEFAULT, &cs_stage.args);
cs_stage.info.user_sgprs_locs = cs_stage.args.user_sgprs_locs; cs_stage.info.user_sgprs_locs = cs_stage.args.user_sgprs_locs;
cs_stage.info.inline_push_constant_mask = cs_stage.args.ac.inline_push_const_mask; cs_stage.info.inline_push_constant_mask = cs_stage.args.ac.inline_push_const_mask;

2
src/amd/vulkan/radv_pipeline_rt.c
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@@ -271,7 +271,7 @@ radv_rt_pipeline_compile(struct radv_ray_tracing_pipeline *pipeline,
rt_stage.args.load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr; rt_stage.args.load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr;
radv_declare_shader_args(device, pipeline_key, &rt_stage.info, rt_stage.stage, false, radv_declare_shader_args(device, pipeline_key, &rt_stage.info, rt_stage.stage, false,
MESA_SHADER_NONE, &rt_stage.args); MESA_SHADER_NONE, RADV_SHADER_TYPE_DEFAULT, &rt_stage.args);
rt_stage.info.user_sgprs_locs = rt_stage.args.user_sgprs_locs; rt_stage.info.user_sgprs_locs = rt_stage.args.user_sgprs_locs;
rt_stage.info.inline_push_constant_mask = rt_stage.args.ac.inline_push_const_mask; rt_stage.info.inline_push_constant_mask = rt_stage.args.ac.inline_push_const_mask;

9
src/amd/vulkan/radv_shader.c
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@@ -2284,8 +2284,8 @@ radv_create_trap_handler_shader(struct radv_device *device)
struct radv_shader_args args; struct radv_shader_args args;
args.explicit_scratch_args = true; args.explicit_scratch_args = true;
args.is_trap_handler_shader = true; radv_declare_shader_args(device, &key, &info, stage, false, MESA_SHADER_NONE,
radv_declare_shader_args(device, &key, &info, stage, false, MESA_SHADER_NONE, &args); RADV_SHADER_TYPE_TRAP_HANDLER, &args);
struct radv_shader_binary *binary = struct radv_shader_binary *binary =
shader_compile(device, &b.shader, 1, stage, &info, &args, &options); shader_compile(device, &b.shader, 1, stage, &info, &args, &options);
@@ -2357,7 +2357,7 @@ radv_create_rt_prolog(struct radv_device *device)
in_args.explicit_scratch_args = true; in_args.explicit_scratch_args = true;
radv_declare_shader_args(device, &pipeline_key, &info, MESA_SHADER_COMPUTE, false, radv_declare_shader_args(device, &pipeline_key, &info, MESA_SHADER_COMPUTE, false,
MESA_SHADER_NONE, &in_args); MESA_SHADER_NONE, RADV_SHADER_TYPE_DEFAULT, &in_args);
radv_declare_rt_shader_args(options.gfx_level, &out_args); radv_declare_rt_shader_args(options.gfx_level, &out_args);
info.user_sgprs_locs = in_args.user_sgprs_locs; info.user_sgprs_locs = in_args.user_sgprs_locs;
@@ -2422,7 +2422,8 @@ radv_create_vs_prolog(struct radv_device *device, const struct radv_vs_prolog_ke
args.explicit_scratch_args = true; args.explicit_scratch_args = true;
radv_declare_shader_args(device, &pipeline_key, &info, key->next_stage, radv_declare_shader_args(device, &pipeline_key, &info, key->next_stage,
key->next_stage != MESA_SHADER_VERTEX, MESA_SHADER_VERTEX, &args); key->next_stage != MESA_SHADER_VERTEX, MESA_SHADER_VERTEX,
RADV_SHADER_TYPE_DEFAULT, &args);
info.user_sgprs_locs = args.user_sgprs_locs; info.user_sgprs_locs = args.user_sgprs_locs;
info.inline_push_constant_mask = args.ac.inline_push_const_mask; info.inline_push_constant_mask = args.ac.inline_push_const_mask;

24
src/amd/vulkan/radv_shader_args.c
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@@ -143,8 +143,9 @@ declare_vs_specific_input_sgprs(const struct radv_shader_info *info, struct radv
if (info->vs.has_prolog) if (info->vs.has_prolog)
add_ud_arg(args, 2, AC_ARG_INT, &args->prolog_inputs, AC_UD_VS_PROLOG_INPUTS); add_ud_arg(args, 2, AC_ARG_INT, &args->prolog_inputs, AC_UD_VS_PROLOG_INPUTS);
if (!args->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || if (args->type != RADV_SHADER_TYPE_GS_COPY &&
(has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) { (stage == MESA_SHADER_VERTEX ||
(has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
if (info->vs.vb_desc_usage_mask) { if (info->vs.vb_desc_usage_mask) {
add_ud_arg(args, 1, AC_ARG_CONST_DESC_PTR, &args->ac.vertex_buffers, add_ud_arg(args, 1, AC_ARG_CONST_DESC_PTR, &args->ac.vertex_buffers,
AC_UD_VS_VERTEX_BUFFERS); AC_UD_VS_VERTEX_BUFFERS);
@@ -166,7 +167,7 @@ declare_vs_input_vgprs(enum amd_gfx_level gfx_level, const struct radv_shader_in
struct radv_shader_args *args, bool merged_vs_tcs) struct radv_shader_args *args, bool merged_vs_tcs)
{ {
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.vertex_id); ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.vertex_id);
if (!args->is_gs_copy_shader) { if (args->type != RADV_SHADER_TYPE_GS_COPY) {
if (info->vs.as_ls || merged_vs_tcs) { if (info->vs.as_ls || merged_vs_tcs) {
if (gfx_level >= GFX11) { if (gfx_level >= GFX11) {
@@ -334,13 +335,14 @@ declare_ngg_sgprs(const struct radv_shader_info *info, struct radv_shader_args *
static void static void
radv_init_shader_args(const struct radv_device *device, gl_shader_stage stage, radv_init_shader_args(const struct radv_device *device, gl_shader_stage stage,
struct radv_shader_args *args) enum radv_shader_type type, struct radv_shader_args *args)
{ {
memset(args, 0, sizeof(*args)); memset(args, 0, sizeof(*args));
args->explicit_scratch_args = !radv_use_llvm_for_stage(device, stage); args->explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
args->remap_spi_ps_input = !radv_use_llvm_for_stage(device, stage); args->remap_spi_ps_input = !radv_use_llvm_for_stage(device, stage);
args->load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr; args->load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr;
args->type = type;
for (int i = 0; i < MAX_SETS; i++) for (int i = 0; i < MAX_SETS; i++)
args->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1; args->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
@@ -370,7 +372,8 @@ static void
declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key, declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key,
const struct radv_shader_info *info, gl_shader_stage stage, const struct radv_shader_info *info, gl_shader_stage stage,
bool has_previous_stage, gl_shader_stage previous_stage, bool has_previous_stage, gl_shader_stage previous_stage,
struct radv_shader_args *args, struct user_sgpr_info *user_sgpr_info) enum radv_shader_type type, struct radv_shader_args *args,
struct user_sgpr_info *user_sgpr_info)
{ {
const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
bool needs_view_index = info->uses_view_index; bool needs_view_index = info->uses_view_index;
@@ -386,7 +389,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
has_previous_stage = true; has_previous_stage = true;
} }
radv_init_shader_args(device, stage, args); radv_init_shader_args(device, stage, type, args);
if (gl_shader_stage_is_rt(stage)) { if (gl_shader_stage_is_rt(stage)) {
radv_declare_rt_shader_args(gfx_level, args); radv_declare_rt_shader_args(gfx_level, args);
@@ -680,9 +683,10 @@ void
radv_declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key, radv_declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key,
const struct radv_shader_info *info, gl_shader_stage stage, const struct radv_shader_info *info, gl_shader_stage stage,
bool has_previous_stage, gl_shader_stage previous_stage, bool has_previous_stage, gl_shader_stage previous_stage,
struct radv_shader_args *args) enum radv_shader_type type, struct radv_shader_args *args)
{ {
declare_shader_args(device, key, info, stage, has_previous_stage, previous_stage, args, NULL); declare_shader_args(device, key, info, stage, has_previous_stage, previous_stage, type, args,
NULL);
if (gl_shader_stage_is_rt(stage)) if (gl_shader_stage_is_rt(stage))
return; return;
@@ -711,7 +715,7 @@ radv_declare_shader_args(const struct radv_device *device, const struct radv_pip
allocate_inline_push_consts(info, &user_sgpr_info); allocate_inline_push_consts(info, &user_sgpr_info);
declare_shader_args(device, key, info, stage, has_previous_stage, previous_stage, args, declare_shader_args(device, key, info, stage, has_previous_stage, previous_stage, type, args,
&user_sgpr_info); &user_sgpr_info);
} }
@@ -721,7 +725,7 @@ radv_declare_ps_epilog_args(const struct radv_device *device, const struct radv_
{ {
const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
radv_init_shader_args(device, MESA_SHADER_FRAGMENT, args); radv_init_shader_args(device, MESA_SHADER_FRAGMENT, RADV_SHADER_TYPE_DEFAULT, args);
ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR, &args->ac.ring_offsets); ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR, &args->ac.ring_offsets);
if (gfx_level < GFX11) if (gfx_level < GFX11)

11
src/amd/vulkan/radv_shader_args.h
View File

@@ -32,6 +32,12 @@
#include "radv_constants.h" #include "radv_constants.h"
#include "radv_shader.h" #include "radv_shader.h"
enum radv_shader_type {
RADV_SHADER_TYPE_DEFAULT,
RADV_SHADER_TYPE_GS_COPY,
RADV_SHADER_TYPE_TRAP_HANDLER,
};
struct radv_shader_args { struct radv_shader_args {
struct ac_shader_args ac; struct ac_shader_args ac;
@@ -79,8 +85,7 @@ struct radv_shader_args {
bool explicit_scratch_args; bool explicit_scratch_args;
bool remap_spi_ps_input; bool remap_spi_ps_input;
bool load_grid_size_from_user_sgpr; bool load_grid_size_from_user_sgpr;
bool is_gs_copy_shader; enum radv_shader_type type;
bool is_trap_handler_shader;
}; };
static inline struct radv_shader_args * static inline struct radv_shader_args *
@@ -95,7 +100,7 @@ struct radv_shader_info;
void radv_declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key, void radv_declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key,
const struct radv_shader_info *info, gl_shader_stage stage, const struct radv_shader_info *info, gl_shader_stage stage,
bool has_previous_stage, gl_shader_stage previous_stage, bool has_previous_stage, gl_shader_stage previous_stage,
struct radv_shader_args *args); enum radv_shader_type type, struct radv_shader_args *args);
void radv_declare_ps_epilog_args(const struct radv_device *device, void radv_declare_ps_epilog_args(const struct radv_device *device,
const struct radv_ps_epilog_key *key, const struct radv_ps_epilog_key *key,