From 6f2dbe6da14a22463e7ca64307767bf31353d74f Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Tue, 29 Nov 2022 13:42:12 +0200 Subject: [PATCH] anv: enable lower_shader_calls vectorizing On Q2RTX RT shaders : Totals from 7 (22.58% of 31) affected shaders: Instrs: 15453 -> 14418 (-6.70%) Cycles: 232647 -> 224959 (-3.30%) Send messages: 574 -> 481 (-16.20%) Spill count: 118 -> 106 (-10.17%) Fill count: 156 -> 140 (-10.26%) Signed-off-by: Lionel Landwerlin Acked-by: Konstantin Seurer Part-of: --- src/intel/compiler/brw_nir.c | 2 +- src/intel/compiler/brw_nir.h | 7 +++++++ src/intel/vulkan/anv_pipeline.c | 2 ++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 81057e36803..d4b0e8c8d3f 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -1123,7 +1123,7 @@ brw_nir_link_shaders(const struct brw_compiler *compiler, } } -static bool +bool brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, unsigned bit_size, unsigned num_components, diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h index b1e07d11e44..4836661b69b 100644 --- a/src/intel/compiler/brw_nir.h +++ b/src/intel/compiler/brw_nir.h @@ -157,6 +157,13 @@ uint32_t brw_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic); enum brw_reg_type brw_type_for_nir_type(const struct intel_device_info *devinfo, nir_alu_type type); +bool brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, + unsigned bit_size, + unsigned num_components, + nir_intrinsic_instr *low, + nir_intrinsic_instr *high, + void *data); + void brw_nir_setup_glsl_uniforms(void *mem_ctx, nir_shader *shader, const struct gl_program *prog, struct brw_stage_prog_data *stage_prog_data, diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 72806ca62e9..6d95005bcd5 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -2468,6 +2468,8 @@ compile_upload_rt_shader(struct anv_ray_tracing_pipeline *pipeline, .address_format = nir_address_format_64bit_global, .stack_alignment = BRW_BTD_STACK_ALIGN, .localized_loads = true, + .vectorizer_callback = brw_nir_should_vectorize_mem, + .vectorizer_data = NULL, }; NIR_PASS(_, nir, nir_lower_shader_calls, &opts,