anv: enable lower_shader_calls vectorizing

On Q2RTX RT shaders :

Totals from 7 (22.58% of 31) affected shaders:
Instrs: 15453 -> 14418 (-6.70%)
Cycles: 232647 -> 224959 (-3.30%)
Send messages: 574 -> 481 (-16.20%)
Spill count: 118 -> 106 (-10.17%)
Fill count: 156 -> 140 (-10.26%)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>
This commit is contained in:
Lionel Landwerlin
2022-11-29 13:42:12 +02:00
committed by Marge Bot
parent 9d0560fe87
commit 6f2dbe6da1
3 changed files with 10 additions and 1 deletions

View File

@@ -1123,7 +1123,7 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
}
}
static bool
bool
brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
unsigned bit_size,
unsigned num_components,

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@@ -157,6 +157,13 @@ uint32_t brw_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic);
enum brw_reg_type brw_type_for_nir_type(const struct intel_device_info *devinfo,
nir_alu_type type);
bool brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
unsigned bit_size,
unsigned num_components,
nir_intrinsic_instr *low,
nir_intrinsic_instr *high,
void *data);
void brw_nir_setup_glsl_uniforms(void *mem_ctx, nir_shader *shader,
const struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,

View File

@@ -2468,6 +2468,8 @@ compile_upload_rt_shader(struct anv_ray_tracing_pipeline *pipeline,
.address_format = nir_address_format_64bit_global,
.stack_alignment = BRW_BTD_STACK_ALIGN,
.localized_loads = true,
.vectorizer_callback = brw_nir_should_vectorize_mem,
.vectorizer_data = NULL,
};
NIR_PASS(_, nir, nir_lower_shader_calls, &opts,