anv: enable lower_shader_calls vectorizing
On Q2RTX RT shaders : Totals from 7 (22.58% of 31) affected shaders: Instrs: 15453 -> 14418 (-6.70%) Cycles: 232647 -> 224959 (-3.30%) Send messages: 574 -> 481 (-16.20%) Spill count: 118 -> 106 (-10.17%) Fill count: 156 -> 140 (-10.26%) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>
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@@ -1123,7 +1123,7 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
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}
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}
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static bool
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bool
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brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
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unsigned bit_size,
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unsigned num_components,
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@@ -157,6 +157,13 @@ uint32_t brw_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic);
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enum brw_reg_type brw_type_for_nir_type(const struct intel_device_info *devinfo,
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nir_alu_type type);
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bool brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
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unsigned bit_size,
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unsigned num_components,
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nir_intrinsic_instr *low,
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nir_intrinsic_instr *high,
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void *data);
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void brw_nir_setup_glsl_uniforms(void *mem_ctx, nir_shader *shader,
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const struct gl_program *prog,
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struct brw_stage_prog_data *stage_prog_data,
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@@ -2468,6 +2468,8 @@ compile_upload_rt_shader(struct anv_ray_tracing_pipeline *pipeline,
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.address_format = nir_address_format_64bit_global,
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.stack_alignment = BRW_BTD_STACK_ALIGN,
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.localized_loads = true,
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.vectorizer_callback = brw_nir_should_vectorize_mem,
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.vectorizer_data = NULL,
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};
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NIR_PASS(_, nir, nir_lower_shader_calls, &opts,
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