From 6e8f3677c7ea3d96596e86990c0fa87b99248a04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Tue, 18 Jan 2022 16:37:53 +0100 Subject: [PATCH] radv: Enable nir_opt_offsets for task shaders. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Timur Kristóf Reviewed-by: Rhys Perry Part-of: --- src/amd/vulkan/radv_pipeline.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 7df2f58717d..4a73eccc4a3 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4504,7 +4504,8 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout ac_nir_lower_global_access(stages[i].nir); radv_nir_lower_abi(stages[i].nir, device->physical_device->rad_info.chip_class, &stages[i].info, &stages[i].args, pipeline_key); - radv_optimize_nir_algebraic(stages[i].nir, io_to_mem || lowered_ngg || i == MESA_SHADER_COMPUTE); + radv_optimize_nir_algebraic( + stages[i].nir, io_to_mem || lowered_ngg || i == MESA_SHADER_COMPUTE || i == MESA_SHADER_TASK); if (stages[i].nir->info.bit_sizes_int & (8 | 16)) { if (device->physical_device->rad_info.chip_class >= GFX8) {