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radv: Enable nir_opt_offsets for task shaders.

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Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
This commit is contained in:
Timur Kristóf
2022-01-18 16:37:53 +01:00
committed by Marge Bot
parent a8bdcf3c92
commit 6e8f3677c7
1 changed files with 2 additions and 1 deletions
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src/amd/vulkan/radv_pipeline.c
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@@ -4504,7 +4504,8 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
ac_nir_lower_global_access(stages[i].nir);
radv_nir_lower_abi(stages[i].nir, device->physical_device->rad_info.chip_class,
&stages[i].info, &stages[i].args, pipeline_key);
radv_optimize_nir_algebraic(stages[i].nir, io_to_mem || lowered_ngg || i == MESA_SHADER_COMPUTE);
radv_optimize_nir_algebraic(
stages[i].nir, io_to_mem || lowered_ngg || i == MESA_SHADER_COMPUTE || i == MESA_SHADER_TASK);
if (stages[i].nir->info.bit_sizes_int & (8 | 16)) {
if (device->physical_device->rad_info.chip_class >= GFX8) {