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intel/eu/gen12: Codegen three-source instruction source and destination regions.

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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez
2018-11-09 14:13:35 -08:00
parent 9fdb67aa09
commit 6e1daba3b4
2 changed files with 42 additions and 24 deletions
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1
src/intel/compiler/brw_eu_defines.h
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@@ -989,6 +989,7 @@ enum PACKED brw_vertical_stride {
enum PACKED gen10_align1_3src_vertical_stride { enum PACKED gen10_align1_3src_vertical_stride {
BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0, BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1,
BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1, BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2, BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3, BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,

27
src/intel/compiler/brw_eu_emit.c
View File

@@ -662,12 +662,17 @@ get_3src_subreg_nr(struct brw_reg reg)
} }
static enum gen10_align1_3src_vertical_stride static enum gen10_align1_3src_vertical_stride
to_3src_align1_vstride(enum brw_vertical_stride vstride) to_3src_align1_vstride(const struct gen_device_info *devinfo,
enum brw_vertical_stride vstride)
{ {
switch (vstride) { switch (vstride) {
case BRW_VERTICAL_STRIDE_0: case BRW_VERTICAL_STRIDE_0:
return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0; return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0;
case BRW_VERTICAL_STRIDE_1:
assert(devinfo->gen >= 12);
return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1;
case BRW_VERTICAL_STRIDE_2: case BRW_VERTICAL_STRIDE_2:
assert(devinfo->gen < 12);
return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2; return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2;
case BRW_VERTICAL_STRIDE_4: case BRW_VERTICAL_STRIDE_4:
return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4; return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4;
@@ -719,6 +724,10 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
assert(dest.file == BRW_GENERAL_REGISTER_FILE || assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
dest.file == BRW_ARCHITECTURE_REGISTER_FILE); dest.file == BRW_ARCHITECTURE_REGISTER_FILE);
if (devinfo->gen >= 12) {
brw_inst_set_3src_a1_dst_reg_file(devinfo, inst, dest.file);
brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
} else {
if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE) { if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE) {
brw_inst_set_3src_a1_dst_reg_file(devinfo, inst, brw_inst_set_3src_a1_dst_reg_file(devinfo, inst,
BRW_ALIGN1_3SRC_ACCUMULATOR); BRW_ALIGN1_3SRC_ACCUMULATOR);
@@ -728,6 +737,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE); BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE);
brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr); brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
} }
}
brw_inst_set_3src_a1_dst_subreg_nr(devinfo, inst, dest.subnr / 8); brw_inst_set_3src_a1_dst_subreg_nr(devinfo, inst, dest.subnr / 8);
brw_inst_set_3src_a1_dst_hstride(devinfo, inst, BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1); brw_inst_set_3src_a1_dst_hstride(devinfo, inst, BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1);
@@ -745,10 +755,10 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
brw_inst_set_3src_a1_src1_type(devinfo, inst, src1.type); brw_inst_set_3src_a1_src1_type(devinfo, inst, src1.type);
brw_inst_set_3src_a1_src2_type(devinfo, inst, src2.type); brw_inst_set_3src_a1_src2_type(devinfo, inst, src2.type);
brw_inst_set_3src_a1_src0_vstride(devinfo, inst, brw_inst_set_3src_a1_src0_vstride(
to_3src_align1_vstride(src0.vstride)); devinfo, inst, to_3src_align1_vstride(devinfo, src0.vstride));
brw_inst_set_3src_a1_src1_vstride(devinfo, inst, brw_inst_set_3src_a1_src1_vstride(
to_3src_align1_vstride(src1.vstride)); devinfo, inst, to_3src_align1_vstride(devinfo, src1.vstride));
/* no vstride on src2 */ /* no vstride on src2 */
brw_inst_set_3src_a1_src0_hstride(devinfo, inst, brw_inst_set_3src_a1_src0_hstride(devinfo, inst,
@@ -790,6 +800,11 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
assert(src2.file == BRW_GENERAL_REGISTER_FILE || assert(src2.file == BRW_GENERAL_REGISTER_FILE ||
src2.file == BRW_IMMEDIATE_VALUE); src2.file == BRW_IMMEDIATE_VALUE);
if (devinfo->gen >= 12) {
brw_inst_set_3src_a1_src0_reg_file(devinfo, inst, src0.file);
brw_inst_set_3src_a1_src1_reg_file(devinfo, inst, src1.file);
brw_inst_set_3src_a1_src2_reg_file(devinfo, inst, src2.file);
} else {
brw_inst_set_3src_a1_src0_reg_file(devinfo, inst, brw_inst_set_3src_a1_src0_reg_file(devinfo, inst,
src0.file == BRW_GENERAL_REGISTER_FILE ? src0.file == BRW_GENERAL_REGISTER_FILE ?
BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE : BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE :
@@ -802,6 +817,8 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
src2.file == BRW_GENERAL_REGISTER_FILE ? src2.file == BRW_GENERAL_REGISTER_FILE ?
BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE : BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE :
BRW_ALIGN1_3SRC_IMMEDIATE_VALUE); BRW_ALIGN1_3SRC_IMMEDIATE_VALUE);
}
} else { } else {
assert(dest.file == BRW_GENERAL_REGISTER_FILE || assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
dest.file == BRW_MESSAGE_REGISTER_FILE); dest.file == BRW_MESSAGE_REGISTER_FILE);