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intel: add a new intrinsic to get the shader stage from bindless shaders

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We'll use this to apply ray tracing operations in our trivial return
shader based on the stage we're in.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
This commit is contained in:
Lionel Landwerlin
2021-10-06 12:15:59 +03:00
committed by Marge Bot
parent b8f087b0e6
commit 6d9ae6ec1e
2 changed files with 13 additions and 0 deletions
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6
src/compiler/nir/nir_intrinsics.py
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@@ -1386,3 +1386,9 @@ system_value("callable_sbt_addr_intel", 1, bit_sizes=[64])
system_value("callable_sbt_stride_intel", 1, bit_sizes=[16])
system_value("leaf_opaque_intel", 1, bit_sizes=[1])
system_value("leaf_procedural_intel", 1, bit_sizes=[1])
# Values :
# 0: AnyHit
# 1: ClosestHit
# 2: Miss
# 3: Intersection
system_value("btd_shader_type_intel", 1)

7
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -4039,6 +4039,13 @@ fs_visitor::nir_emit_bs_intrinsic(const fs_builder &bld,
bld.MOV(dest, retype(brw_vec1_grf(2, 2), dest.type));
break;
case nir_intrinsic_load_btd_shader_type_intel: {
fs_reg ud_dest = retype(dest, BRW_REGISTER_TYPE_UD);
bld.MOV(ud_dest, retype(brw_vec1_grf(0, 3), ud_dest.type));
bld.AND(ud_dest, ud_dest, brw_imm_ud(0xf));
break;
}
default:
nir_emit_intrinsic(bld, instr);
break;