From 6d93f4f867cfccfba06a01976e179401e70e9cb9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Feb 2023 11:36:58 +0100 Subject: [PATCH] freedreno: Add A2xx REG_A2XX_RBBM_PM_OVERRIDE2 bitfields Required for good-looking kernel code Signed-off-by: Konrad Dybcio Part-of: --- ...cification.basic_teximage2d.rgba16f_2d.log | 76 +++++++++---------- src/freedreno/registers/adreno/a2xx.xml | 15 +++- 2 files changed, 52 insertions(+), 39 deletions(-) diff --git a/src/freedreno/.gitlab-ci/reference/dEQP-GLES2.functional.texture.specification.basic_teximage2d.rgba16f_2d.log b/src/freedreno/.gitlab-ci/reference/dEQP-GLES2.functional.texture.specification.basic_teximage2d.rgba16f_2d.log index 8ade566661d..6fe28642906 100644 --- a/src/freedreno/.gitlab-ci/reference/dEQP-GLES2.functional.texture.specification.basic_teximage2d.rgba16f_2d.log +++ b/src/freedreno/.gitlab-ci/reference/dEQP-GLES2.functional.texture.specification.basic_teximage2d.rgba16f_2d.log @@ -19,7 +19,7 @@ cmdstream[0]: 124 dwords 0122d02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122d034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -247,7 +247,7 @@ cmdstream[0]: 124 dwords num_indices: 1407 draw[0] register values !+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } -!+ 00000fff RBBM_PM_OVERRIDE2: 0xfff +!+ 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000009 CP_SCRATCH_REG6: 9 :0,0,9,5 @@ -397,7 +397,7 @@ cmdstream[1]: 124 dwords 0122f02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122f034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -625,7 +625,7 @@ cmdstream[1]: 124 dwords num_indices: 1407 draw[1] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 0000000f CP_SCRATCH_REG6: 15 :0,0,15,11 @@ -775,7 +775,7 @@ cmdstream[2]: 124 dwords 0122d02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122d034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -1003,7 +1003,7 @@ cmdstream[2]: 124 dwords num_indices: 1407 draw[2] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000015 CP_SCRATCH_REG6: 21 :0,0,21,17 @@ -1153,7 +1153,7 @@ cmdstream[3]: 124 dwords 0122f02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122f034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -1381,7 +1381,7 @@ cmdstream[3]: 124 dwords num_indices: 1407 draw[3] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 0000001b CP_SCRATCH_REG6: 27 :0,0,27,23 @@ -1531,7 +1531,7 @@ cmdstream[4]: 124 dwords 0122d02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122d034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -1759,7 +1759,7 @@ cmdstream[4]: 124 dwords num_indices: 1407 draw[4] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000021 CP_SCRATCH_REG6: 33 :0,0,33,29 @@ -1909,7 +1909,7 @@ cmdstream[5]: 124 dwords 0122f02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122f034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -2137,7 +2137,7 @@ cmdstream[5]: 124 dwords num_indices: 1407 draw[5] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000027 CP_SCRATCH_REG6: 39 :0,0,39,35 @@ -2287,7 +2287,7 @@ cmdstream[6]: 124 dwords 0122d02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122d034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -2515,7 +2515,7 @@ cmdstream[6]: 124 dwords num_indices: 1407 draw[6] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 0000002d CP_SCRATCH_REG6: 45 :0,0,45,41 @@ -2665,7 +2665,7 @@ cmdstream[7]: 124 dwords 0122f02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122f034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -2893,7 +2893,7 @@ cmdstream[7]: 124 dwords num_indices: 1407 draw[7] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000033 CP_SCRATCH_REG6: 51 :0,0,51,47 @@ -3043,7 +3043,7 @@ cmdstream[8]: 124 dwords 0122d02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122d034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -3271,7 +3271,7 @@ cmdstream[8]: 124 dwords num_indices: 1407 draw[8] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000039 CP_SCRATCH_REG6: 57 :0,0,57,53 @@ -3421,7 +3421,7 @@ cmdstream[9]: 340 dwords 0110a02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0110a034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -3641,7 +3641,7 @@ cmdstream[9]: 340 dwords num_indices: 18011360 draw[9] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000043 CP_SCRATCH_REG6: 67 :0,0,67,61 @@ -4660,7 +4660,7 @@ NEEDS WFI: CP_PERFMON_CNTL (444) NEEDS WFI: RBBM_PM_OVERRIDE1 (39c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } NEEDS WFI: RBBM_PM_OVERRIDE2 (39d) - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122f034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) NEEDS WFI: TP0_CHICKEN (e1e) @@ -4893,7 +4893,7 @@ NEEDS WFI: CP_SCRATCH_REG7 (57f) num_indices: 1407 draw[14] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000059 CP_SCRATCH_REG6: 89 :0,0,89,85 @@ -5046,7 +5046,7 @@ cmdstream[11]: 124 dwords 0110c02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0110c034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -5276,7 +5276,7 @@ cmdstream[11]: 124 dwords num_indices: 18011596 draw[15] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 0000005f CP_SCRATCH_REG6: 95 :0,0,95,91 @@ -5426,7 +5426,7 @@ cmdstream[12]: 124 dwords 0122d02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122d034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -5654,7 +5654,7 @@ cmdstream[12]: 124 dwords num_indices: 1407 draw[16] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000065 CP_SCRATCH_REG6: 101 :0,0,101,97 @@ -5804,7 +5804,7 @@ cmdstream[13]: 124 dwords 0110a02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0110a034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -6034,7 +6034,7 @@ cmdstream[13]: 124 dwords num_indices: 18011832 draw[17] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 0000006b CP_SCRATCH_REG6: 107 :0,0,107,103 @@ -6184,7 +6184,7 @@ cmdstream[14]: 124 dwords 0122f02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122f034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -6412,7 +6412,7 @@ cmdstream[14]: 124 dwords num_indices: 1407 draw[18] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000071 CP_SCRATCH_REG6: 113 :0,0,113,109 @@ -6562,7 +6562,7 @@ cmdstream[15]: 124 dwords 0110c02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0110c034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -6792,7 +6792,7 @@ cmdstream[15]: 124 dwords num_indices: 18012068 draw[19] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000077 CP_SCRATCH_REG6: 119 :0,0,119,115 @@ -6942,7 +6942,7 @@ cmdstream[16]: 124 dwords 0122d02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122d034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -7170,7 +7170,7 @@ cmdstream[16]: 124 dwords num_indices: 1407 draw[20] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 0000007d CP_SCRATCH_REG6: 125 :0,0,125,121 @@ -7320,7 +7320,7 @@ cmdstream[17]: 124 dwords 0110a02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0110a034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -7550,7 +7550,7 @@ cmdstream[17]: 124 dwords num_indices: 18012304 draw[21] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000083 CP_SCRATCH_REG6: 131 :0,0,131,127 @@ -7700,7 +7700,7 @@ cmdstream[18]: 124 dwords 0122f02c: 0000: 00000444 00000000 write RBBM_PM_OVERRIDE1 (039c) RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - RBBM_PM_OVERRIDE2: 0xfff + RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } 0122f034: 0000: 0001039c ffffffff 00000fff write TP0_CHICKEN (0e1e) TP0_CHICKEN: 0x2 @@ -7928,7 +7928,7 @@ cmdstream[18]: 124 dwords num_indices: 1407 draw[22] register values + ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE } - + 00000fff RBBM_PM_OVERRIDE2: 0xfff + + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE } + 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET } !+ 00000089 CP_SCRATCH_REG6: 137 :0,0,137,133 diff --git a/src/freedreno/registers/adreno/a2xx.xml b/src/freedreno/registers/adreno/a2xx.xml index 641c9974f66..f49f65df781 100644 --- a/src/freedreno/registers/adreno/a2xx.xml +++ b/src/freedreno/registers/adreno/a2xx.xml @@ -1122,7 +1122,20 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> - + + + + + + + + + + + + + +