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intel/isl: Avoid tiling some 16K-wide render targets

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Fix rendering issues on BDW and SKL.

Fixes: 0288fe8d04
("i965/miptree: Use the correct BLT pitch")

Fixes the following regressions seen

exclusively on SKL:
* KHR-GL46.texture_barrier_ARB.disjoint-texels
* KHR-GL46.texture_barrier_ARB.overlapping-texels
* KHR-GL46.texture_barrier.disjoint-texels
* KHR-GL46.texture_barrier.overlapping-texels

and both on BDW and SKL:
* GTF-GL46.gtf21.GL2FixedTests.buffer_corners.buffer_corners
* GTF-GL46.gtf21.GL2FixedTests.stencil_plane_corners.stencil_plane_corners

v2: Note the fixed tests (Andres).
    Don't cause failures with multisampled buffers (Andres).
    Don't hamper SKL GT4 (Ken).
v3: Fix the Fixes tag (Dylan).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107359
Cc: <mesa-stable@lists.freedesktop.org>
Tested-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Nanley Chery
2018-07-27 15:34:05 -07:00
parent b041fc0649
commit 6d80b0b4ba
1 changed files with 23 additions and 0 deletions
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23
src/intel/isl/isl_gen7.c
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@@ -294,6 +294,29 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
*/
if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb >= 128)
*flags &= ~ISL_TILING_Y0_BIT;
/* From the BDW and SKL PRMs, Volume 2d,
* RENDER_SURFACE_STATE::Width - Programming Notes:
*
* A known issue exists if a primitive is rendered to the first 2 rows and
* last 2 columns of a 16K width surface. If any geometry is drawn inside
* this square it will be copied to column X=2 and X=3 (arrangement on Y
* position will stay the same). If any geometry exceeds the boundaries of
* this 2x2 region it will be drawn normally. The issue also only occurs
* if the surface has TileMode != Linear.
*
* [Internal documentation notes that this issue isn't present on SKL GT4.]
* To prevent this rendering corruption, only allow linear tiling for
* surfaces with widths greater than 16K-2 pixels.
*
* TODO: Is this an issue for multisampled surfaces as well?
*/
if (info->width > 16382 && info->samples == 1 &&
info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT &&
(ISL_DEV_GEN(dev) == 8 ||
(dev->info->is_skylake && dev->info->gt != 4))) {
*flags &= ISL_TILING_LINEAR_BIT;
}
}
void