From 6d77dfa75d334aace59839885ea81a767ac94c4b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Thu, 27 Jun 2024 14:11:30 -0700 Subject: [PATCH] intel/dev: Use GPU WB PAT for Xe2 writecombining MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit So for this entry we want the CPU mapping to be WC but GPU caches can be WB. This way GPU don't need to snoop to CPU caches and at the end of workloads L3 cache is flushed, so CPU access is coherent after get the signal that workload was finished. With this the transient(XD) L3 flushes will only affect displayable buffers. Ref: Bspec 71582 (r59285) Reviewed-by: Jordan Justen Reviewed-by: Jianxun Zhang Signed-off-by: José Roberto de Souza Part-of: --- src/intel/dev/intel_device_info.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/dev/intel_device_info.c b/src/intel/dev/intel_device_info.c index 29d83f1bed6..38848500521 100644 --- a/src/intel/dev/intel_device_info.c +++ b/src/intel/dev/intel_device_info.c @@ -1236,8 +1236,8 @@ static const struct intel_device_info intel_device_info_arl_h = { .scanout = PAT_ENTRY(6, WC), \ /* CPU: WB, GPU: PAT 0 => WB, 0WAY */ \ .writeback_incoherent = PAT_ENTRY(0, WB), \ - /* CPU: WC, GPU: PAT 6 => XD */ \ - .writecombining = PAT_ENTRY(6, WC), \ + /* CPU: WC, GPU: PAT 0 => WB */ \ + .writecombining = PAT_ENTRY(0, WC), \ /* CPU: WC, GPU: PAT 11 => XD, compressed */ \ .compressed = PAT_ENTRY(11, WC) \ }, \