intel/dev: Use GPU WB PAT for Xe2 writecombining

So for this entry we want the CPU mapping to be WC but GPU caches
can be WB.
This way GPU don't need to snoop to CPU caches and at the end of
workloads L3 cache is flushed, so CPU access is coherent after get
the signal that workload was finished.

With this the transient(XD) L3 flushes will only affect displayable
buffers.

Ref: Bspec 71582 (r59285)
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29950>

src/intel/dev/intel_device_info.c

@@ -1236,8 +1236,8 @@ static const struct intel_device_info intel_device_info_arl_h = {
       .scanout = PAT_ENTRY(6, WC),                              \
       /* CPU: WB, GPU: PAT 0 => WB, 0WAY */                     \
       .writeback_incoherent = PAT_ENTRY(0, WB),                 \
-      /* CPU: WC, GPU: PAT 6 => XD */                           \
-      .writecombining = PAT_ENTRY(6, WC),                       \
+      /* CPU: WC, GPU: PAT 0 => WB */                           \
+      .writecombining = PAT_ENTRY(0, WC),                       \
       /* CPU: WC, GPU: PAT 11 => XD, compressed */              \
       .compressed = PAT_ENTRY(11, WC)                           \
    },                                                           \