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anv: Disable stencil writes when both write masks are zero

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Vulkan doesn't have a stencilWriteEnable bit like it does for depth.
Instead, you have a stencil mask.  Since the stencil mask is handled as
dynamic state, we have to handle it later during command buffer
construction.  This, combined with a later commit, seems to help Dota2
on my Broadwell GT3e desktop by a couple percent because it allows the
hardware to move the depth and stencil writes to early in more cases.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
This commit is contained in:
Jason Ekstrand
2016-12-07 20:31:12 -08:00
parent 114c281e70
commit 6ce8592836
4 changed files with 17 additions and 2 deletions
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6
src/intel/vulkan/genX_pipeline.c
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@@ -663,12 +663,15 @@ emit_ds_state(struct anv_pipeline *pipeline,
/* We're going to OR this together with the dynamic state. We need
* to make sure it's initialized to something useful.
*/
pipeline->writes_stencil = false;
memset(depth_stencil_dw, 0, sizeof(depth_stencil_dw));
return;
}
/* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
pipeline->writes_stencil = info->stencilTestEnable;
#if GEN_GEN <= 7
struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
#else
@@ -680,7 +683,6 @@ emit_ds_state(struct anv_pipeline *pipeline,
.DoubleSidedStencilEnable = true,
.StencilTestEnable = info->stencilTestEnable,
.StencilBufferWriteEnable = info->stencilTestEnable,
.StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
@@ -707,7 +709,7 @@ emit_ds_state(struct anv_pipeline *pipeline,
}
if (!(aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) {
depth_stencil.StencilBufferWriteEnable = false;
pipeline->writes_stencil = false;
depth_stencil.StencilTestFunction = PREFILTEROPALWAYS;
depth_stencil.BackfaceStencilTestFunction = PREFILTEROPALWAYS;
}