anv: Disable stencil writes when both write masks are zero

Vulkan doesn't have a stencilWriteEnable bit like it does for depth.
Instead, you have a stencil mask.  Since the stencil mask is handled as
dynamic state, we have to handle it later during command buffer
construction.  This, combined with a later commit, seems to help Dota2
on my Broadwell GT3e desktop by a couple percent because it allows the
hardware to move the depth and stencil writes to early in more cases.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

src/intel/vulkan/anv_private.h

@@ -1471,6 +1471,7 @@ struct anv_pipeline {
 
    uint32_t                                     cs_right_mask;
 
+   bool                                         writes_stencil;
    bool                                         depth_clamp_enable;
 
    struct {