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ac/nir: use nir_intrinsic_load_hs_out_patch_data_offset_amd in tess lower

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radeonsi load this from SGPR arg, can't use static value because TCS output
and TES input may not match (TCS output is not a key for TES) and
determined in runtime.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
This commit is contained in:
Qiang Yu
2022-05-23 17:26:00 +08:00
committed by Marge Bot
parent fdf589321c
commit 6ccb9634de
3 changed files with 5 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/amd/common/ac_nir.h
View File

@@ -93,8 +93,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
void
ac_nir_lower_tes_inputs_to_mem(nir_shader *shader,
ac_nir_map_io_driver_location map,
unsigned num_reserved_tcs_outputs);
ac_nir_map_io_driver_location map);
void
ac_nir_lower_es_outputs_to_mem(nir_shader *shader,

13
src/amd/common/ac_nir_lower_tess_io_to_mem.c
View File

@@ -107,7 +107,7 @@
* attr 1 of patch 0 vertex 2
* ...
* ...
* per-patch attr 0 of patch 0
* per-patch attr 0 of patch 0 <─── hs_out_patch_data_offset_amd
* per-patch attr 0 of patch 1
* per-patch attr 0 of patch 2 <─── hs_per_patch_output_vmem_offset (attribute slot = 0, rel_patch_id = 2)
* ...
@@ -373,13 +373,8 @@ hs_per_patch_output_vmem_offset(nir_builder *b,
nir_intrinsic_instr *intrin,
unsigned const_base_offset)
{
nir_ssa_def *out_vertices_per_patch = b->shader->info.stage == MESA_SHADER_TESS_CTRL
? nir_imm_int(b, b->shader->info.tess.tcs_vertices_out)
: nir_load_patch_vertices_in(b);
nir_ssa_def *tcs_num_patches = nir_load_tcs_num_patches_amd(b);
nir_ssa_def *per_vertex_output_patch_size = nir_imul_imm(b, out_vertices_per_patch, st->tcs_num_reserved_outputs * 16u);
nir_ssa_def *per_patch_data_offset = nir_imul(b, tcs_num_patches, per_vertex_output_patch_size);
nir_ssa_def *per_patch_data_offset = nir_load_hs_out_patch_data_offset_amd(b);
nir_ssa_def * off = intrin
? ac_nir_calc_io_offset(b, intrin, nir_imul_imm(b, tcs_num_patches, 16u), 4u, st->map_io)
@@ -724,13 +719,11 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
void
ac_nir_lower_tes_inputs_to_mem(nir_shader *shader,
ac_nir_map_io_driver_location map,
unsigned num_reserved_tcs_outputs)
ac_nir_map_io_driver_location map)
{
assert(shader->info.stage == MESA_SHADER_TESS_EVAL);
lower_tess_io_state state = {
.tcs_num_reserved_outputs = num_reserved_tcs_outputs,
.map_io = map,
};

2
src/amd/vulkan/radv_shader.c
View File

@@ -1128,7 +1128,7 @@ radv_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *sta
return true;
} else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
NIR_PASS_V(nir, ac_nir_lower_tes_inputs_to_mem, NULL, info->tes.num_linked_inputs);
NIR_PASS_V(nir, ac_nir_lower_tes_inputs_to_mem, NULL);
if (info->tes.as_es) {
NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem, NULL,