i965: Add norbc debug option

This INTEL_DEBUG option disables lossless compression (also known
as render buffer compression).

v2: (Matt) Use likely(!lossless_compression_disabled) instead of
           !likely(lossless_compression_disabled)
    (Grazvydas) Update docs/envvars.html

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Topi Pohjolainen
2016-05-31 16:47:50 +03:00
parent 30e9e6bd07
commit 6ca118d2f4
4 changed files with 5 additions and 0 deletions

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@@ -166,6 +166,7 @@ See the <a href="xlibdriver.html">Xlib software driver page</a> for details.
<li>vec4 - force vec4 mode in vertex shader</li>
<li>spill_fs - force spilling of all registers in the scalar backend (useful to debug spilling code)</li>
<li>spill_vec4 - force spilling of all registers in the vec4 backend (useful to debug spilling code)</li>
<li>norbc - disable single sampled render buffer compression</li>
</ul>
</ul>

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@@ -80,6 +80,7 @@ static const struct debug_control debug_control[] = {
{ "tes", DEBUG_TES },
{ "l3", DEBUG_L3 },
{ "do32", DEBUG_DO32 },
{ "norbc", DEBUG_NO_RBC },
{ NULL, 0 }
};

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@@ -73,6 +73,7 @@ extern uint64_t INTEL_DEBUG;
#define DEBUG_TES (1ull << 37)
#define DEBUG_L3 (1ull << 38)
#define DEBUG_DO32 (1ull << 39)
#define DEBUG_NO_RBC (1ull << 40)
#ifdef HAVE_ANDROID_PLATFORM
#define LOG_TAG "INTEL-MESA"

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@@ -1620,7 +1620,9 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
* single-sampled buffers. Disabling compression allows us to skip
* resolves.
*/
const bool lossless_compression_disabled = INTEL_DEBUG & DEBUG_NO_RBC;
const bool is_lossless_compressed =
unlikely(!lossless_compression_disabled) &&
brw->gen >= 9 && !mt->is_scanout &&
intel_miptree_supports_lossless_compressed(brw, mt);