diff --git a/docs/envvars.html b/docs/envvars.html
index 253aaf26dcd..ed957bd1999 100644
--- a/docs/envvars.html
+++ b/docs/envvars.html
@@ -166,6 +166,7 @@ See the <a href="xlibdriver.html">Xlib software driver page</a> for details.
    <li>vec4 - force vec4 mode in vertex shader</li>
    <li>spill_fs - force spilling of all registers in the scalar backend (useful to debug spilling code)</li>
    <li>spill_vec4 - force spilling of all registers in the vec4 backend (useful to debug spilling code)</li>
+   <li>norbc - disable single sampled render buffer compression</li>
 </ul>
 </ul>
 
diff --git a/src/mesa/drivers/dri/i965/intel_debug.c b/src/mesa/drivers/dri/i965/intel_debug.c
index 2589c43ab5e..33e840293a2 100644
--- a/src/mesa/drivers/dri/i965/intel_debug.c
+++ b/src/mesa/drivers/dri/i965/intel_debug.c
@@ -80,6 +80,7 @@ static const struct debug_control debug_control[] = {
    { "tes",         DEBUG_TES },
    { "l3",          DEBUG_L3 },
    { "do32",        DEBUG_DO32 },
+   { "norbc",       DEBUG_NO_RBC },
    { NULL,    0 }
 };
 
diff --git a/src/mesa/drivers/dri/i965/intel_debug.h b/src/mesa/drivers/dri/i965/intel_debug.h
index 22ad83480da..f407b6a3cb7 100644
--- a/src/mesa/drivers/dri/i965/intel_debug.h
+++ b/src/mesa/drivers/dri/i965/intel_debug.h
@@ -73,6 +73,7 @@ extern uint64_t INTEL_DEBUG;
 #define DEBUG_TES                 (1ull << 37)
 #define DEBUG_L3                  (1ull << 38)
 #define DEBUG_DO32                (1ull << 39)
+#define DEBUG_NO_RBC              (1ull << 40)
 
 #ifdef HAVE_ANDROID_PLATFORM
 #define LOG_TAG "INTEL-MESA"
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 3b032c7b0fa..b6265dc3a65 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1620,7 +1620,9 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
     * single-sampled buffers. Disabling compression allows us to skip
     * resolves.
     */
+   const bool lossless_compression_disabled = INTEL_DEBUG & DEBUG_NO_RBC;
    const bool is_lossless_compressed =
+      unlikely(!lossless_compression_disabled) &&
       brw->gen >= 9 && !mt->is_scanout &&
       intel_miptree_supports_lossless_compressed(brw, mt);