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intel/fs: Perform 64-bit SEL_EXEC lowering in the lower_regioning pass.

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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
This commit is contained in:
Francisco Jerez
2021-12-20 14:33:45 -08:00
committed by Marge Bot
parent 9449b71bdd
commit 6c8782c135
2 changed files with 15 additions and 19 deletions
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25
src/intel/compiler/brw_fs_generator.cpp
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@@ -2447,25 +2447,12 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
case SHADER_OPCODE_SEL_EXEC:
assert(inst->force_writemask_all);
if (type_sz(dst.type) > 4 && !devinfo->has_64bit_float) {
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_UD, 0),
subscript(src[1], BRW_REGISTER_TYPE_UD, 0));
brw_set_default_swsb(p, tgl_swsb_null());
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_UD, 1),
subscript(src[1], BRW_REGISTER_TYPE_UD, 1));
brw_set_default_mask_control(p, BRW_MASK_ENABLE);
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_UD, 0),
subscript(src[0], BRW_REGISTER_TYPE_UD, 0));
brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_UD, 1),
subscript(src[0], BRW_REGISTER_TYPE_UD, 1));
} else {
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, dst, src[1]);
brw_set_default_mask_control(p, BRW_MASK_ENABLE);
brw_set_default_swsb(p, tgl_swsb_null());
brw_MOV(p, dst, src[0]);
}
assert(devinfo->has_64bit_float || type_sz(dst.type) <= 4);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, dst, src[1]);
brw_set_default_mask_control(p, BRW_MASK_ENABLE);
brw_set_default_swsb(p, tgl_swsb_null());
brw_MOV(p, dst, src[0]);
break;
case SHADER_OPCODE_QUAD_SWIZZLE: