radv: add and use radv_vs_input_alpha_adjust

Unlike ac_fetch_format, this enum can be packed into two bits.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>

src/amd/compiler/aco_instruction_selection.cpp

@@ -4969,11 +4969,11 @@ get_fetch_data_format(isel_context* ctx, const ac_data_format_info* vtx_info, un
 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  * so we may need to fix it up. */
 Temp
-adjust_vertex_fetch_alpha(isel_context* ctx, unsigned adjustment, Temp alpha)
+adjust_vertex_fetch_alpha(isel_context* ctx, enum radv_vs_input_alpha_adjust adjustment, Temp alpha)
 {
    Builder bld(ctx->program, ctx->block);
 
-   if (adjustment == AC_FETCH_FORMAT_SSCALED)
+   if (adjustment == ALPHA_ADJUST_SSCALED)
       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
 
    /* For the integer-like cases, do a natural sign extension.
@@ -4982,15 +4982,15 @@ adjust_vertex_fetch_alpha(isel_context* ctx, unsigned adjustment, Temp alpha)
     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
     * exponent.
     */
-   unsigned offset = adjustment == AC_FETCH_FORMAT_SNORM ? 23u : 0u;
+   unsigned offset = adjustment == ALPHA_ADJUST_SNORM ? 23u : 0u;
    alpha =
       bld.vop3(aco_opcode::v_bfe_i32, bld.def(v1), alpha, Operand::c32(offset), Operand::c32(2u));
 
    /* Convert back to the right type. */
-   if (adjustment == AC_FETCH_FORMAT_SNORM) {
+   if (adjustment == ALPHA_ADJUST_SNORM) {
       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
       alpha = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand::c32(0xbf800000u), alpha);
-   } else if (adjustment == AC_FETCH_FORMAT_SSCALED) {
+   } else if (adjustment == ALPHA_ADJUST_SSCALED) {
       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
    }
 
@@ -5021,7 +5021,8 @@ visit_load_input(isel_context* ctx, nir_intrinsic_instr* instr)
       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
       unsigned binding_align = ctx->options->key.vs.vertex_binding_align[attrib_binding];
-      enum ac_fetch_format alpha_adjust = ctx->options->key.vs.vertex_alpha_adjust[location];
+      enum radv_vs_input_alpha_adjust alpha_adjust =
+         ctx->options->key.vs.vertex_alpha_adjust[location];
 
       unsigned dfmt = attrib_format & 0xf;
       unsigned nfmt = (attrib_format >> 4) & 0x7;
@@ -5157,7 +5158,7 @@ visit_load_input(isel_context* ctx, nir_intrinsic_instr* instr)
 
          Temp fetch_dst;
          if (channel_start == 0 && fetch_bytes == dst.bytes() && !post_shuffle && !expanded &&
-             (alpha_adjust == AC_FETCH_FORMAT_NONE || num_channels <= 3)) {
+             (alpha_adjust == ALPHA_ADJUST_NONE || num_channels <= 3)) {
             direct_fetch = true;
             fetch_dst = dst;
          } else {
@@ -5206,7 +5207,7 @@ visit_load_input(isel_context* ctx, nir_intrinsic_instr* instr)
             unsigned idx = i + component;
             if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) {
                Temp channel = channels[swizzle[idx]];
-               if (idx == 3 && alpha_adjust != AC_FETCH_FORMAT_NONE)
+               if (idx == 3 && alpha_adjust != ALPHA_ADJUST_NONE)
                   channel = adjust_vertex_fetch_alpha(ctx, alpha_adjust, channel);
                vec->operands[i] = Operand(channel);
 

src/amd/vulkan/radv_nir_to_llvm.c

@@ -606,14 +606,14 @@ radv_get_sampler_desc(struct ac_shader_abi *abi, unsigned descriptor_set, unsign
 static LLVMValueRef
 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx, unsigned adjustment, LLVMValueRef alpha)
 {
-   if (adjustment == AC_FETCH_FORMAT_NONE)
+   if (adjustment == ALPHA_ADJUST_NONE)
       return alpha;
 
    LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
 
    alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
 
-   if (adjustment == AC_FETCH_FORMAT_SSCALED)
+   if (adjustment == ALPHA_ADJUST_SSCALED)
       alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
    else
       alpha = ac_to_integer(&ctx->ac, alpha);
@@ -626,17 +626,17 @@ adjust_vertex_fetch_alpha(struct radv_shader_context *ctx, unsigned adjustment,
     */
    alpha =
       LLVMBuildShl(ctx->ac.builder, alpha,
-                   adjustment == AC_FETCH_FORMAT_SNORM ? LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
+                   adjustment == ALPHA_ADJUST_SNORM ? LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
    alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
 
    /* Convert back to the right type. */
-   if (adjustment == AC_FETCH_FORMAT_SNORM) {
+   if (adjustment == ALPHA_ADJUST_SNORM) {
       LLVMValueRef clamp;
       LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
       alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
       clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
       alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
-   } else if (adjustment == AC_FETCH_FORMAT_SSCALED) {
+   } else if (adjustment == ALPHA_ADJUST_SSCALED) {
       alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
    }
 

src/amd/vulkan/radv_pipeline.c

@@ -2639,22 +2639,22 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline,
             radv_get_attrib_stride(input_state, desc->binding);
       }
 
-      enum ac_fetch_format adjust = AC_FETCH_FORMAT_NONE;
+      enum radv_vs_input_alpha_adjust adjust = ALPHA_ADJUST_NONE;
       if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
           pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
          VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
          switch (format) {
          case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
          case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
-            adjust = AC_FETCH_FORMAT_SNORM;
+            adjust = ALPHA_ADJUST_SNORM;
             break;
          case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
          case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
-            adjust = AC_FETCH_FORMAT_SSCALED;
+            adjust = ALPHA_ADJUST_SSCALED;
             break;
          case VK_FORMAT_A2R10G10B10_SINT_PACK32:
          case VK_FORMAT_A2B10G10R10_SINT_PACK32:
-            adjust = AC_FETCH_FORMAT_SINT;
+            adjust = ALPHA_ADJUST_SINT;
             break;
          default:
             break;

src/amd/vulkan/radv_private.h

@@ -74,6 +74,7 @@
 #include "radv_constants.h"
 #include "radv_descriptor_set.h"
 #include "radv_radeon_winsys.h"
+#include "radv_shader.h"
 #include "sid.h"
 
 /* Pre-declarations needed for WSI entrypoints */

src/amd/vulkan/radv_shader.h

@@ -47,6 +47,13 @@ struct radv_pipeline;
 struct radv_pipeline_cache;
 struct radv_pipeline_key;
 
+enum radv_vs_input_alpha_adjust {
+   ALPHA_ADJUST_NONE = 0,
+   ALPHA_ADJUST_SNORM = 1,
+   ALPHA_ADJUST_SSCALED = 2,
+   ALPHA_ADJUST_SINT = 3,
+};
+
 struct radv_pipeline_key {
    uint32_t has_multiview_view_index : 1;
    uint32_t optimisations_disabled : 1;
@@ -61,7 +68,7 @@ struct radv_pipeline_key {
       uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
       uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
       uint8_t vertex_binding_align[MAX_VBS];
-      enum ac_fetch_format vertex_alpha_adjust[MAX_VERTEX_ATTRIBS];
+      enum radv_vs_input_alpha_adjust vertex_alpha_adjust[MAX_VERTEX_ATTRIBS];
       uint32_t vertex_post_shuffle;
       uint32_t provoking_vtx_last : 1;
       uint8_t topology;