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intel: enable existing workaround for ICL platform

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Patch changes comment to refer to the lineage 14014097488, this
workaround applies for ICL as well.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20952>
This commit is contained in:
Tapani Pälli
2023-01-27 09:42:10 +02:00
committed by Marge Bot
parent 7e072cfba2
commit 6bdc29e2e6
3 changed files with 6 additions and 6 deletions
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4
src/gallium/drivers/iris/iris_state.c
View File

@@ -6653,7 +6653,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
if (zres) if (zres)
genX(emit_depth_state_workarounds)(ice, batch, &zres->surf); genX(emit_depth_state_workarounds)(ice, batch, &zres->surf);
if (GFX_VER >= 12) { if (GFX_VER >= 11) {
/* Wa_1408224581 /* Wa_1408224581
* *
* Workaround: Gfx12LP Astep only An additional pipe control with * Workaround: Gfx12LP Astep only An additional pipe control with
@@ -6661,7 +6661,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
* have an additional pipe control after the stencil state whenever * have an additional pipe control after the stencil state whenever
* the surface state bits of this state is changing). * the surface state bits of this state is changing).
* *
* This also seems sufficient to handle Wa_14014148106. * This also seems sufficient to handle Wa_14014097488.
*/ */
iris_emit_pipe_control_write(batch, "WA for stencil state", iris_emit_pipe_control_write(batch, "WA for stencil state",
PIPE_CONTROL_WRITE_IMMEDIATE, PIPE_CONTROL_WRITE_IMMEDIATE,

4
src/intel/blorp/blorp_genX_exec.h
View File

@@ -1761,7 +1761,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
isl_emit_depth_stencil_hiz_s(isl_dev, dw, &info); isl_emit_depth_stencil_hiz_s(isl_dev, dw, &info);
#if GFX_VER >= 12 #if GFX_VER >= 11
/* Wa_1408224581 /* Wa_1408224581
* *
* Workaround: Gfx12LP Astep only An additional pipe control with * Workaround: Gfx12LP Astep only An additional pipe control with
@@ -1769,7 +1769,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
* have an additional pipe control after the stencil state whenever * have an additional pipe control after the stencil state whenever
* the surface state bits of this state is changing). * the surface state bits of this state is changing).
* *
* This also seems sufficient to handle Wa_14014148106. * This also seems sufficient to handle Wa_14014097488.
*/ */
blorp_emit(batch, GENX(PIPE_CONTROL), pc) { blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
pc.PostSyncOperation = WriteImmediateData; pc.PostSyncOperation = WriteImmediateData;

4
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -6842,7 +6842,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
if (info.depth_surf) if (info.depth_surf)
genX(cmd_buffer_emit_gfx12_depth_wa)(cmd_buffer, info.depth_surf); genX(cmd_buffer_emit_gfx12_depth_wa)(cmd_buffer, info.depth_surf);
if (GFX_VER >= 12) { if (GFX_VER >= 11) {
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT; cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
@@ -6853,7 +6853,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
* have an additional pipe control after the stencil state whenever * have an additional pipe control after the stencil state whenever
* the surface state bits of this state is changing). * the surface state bits of this state is changing).
* *
* This also seems sufficient to handle Wa_14014148106. * This also seems sufficient to handle Wa_14014097488.
*/ */
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.PostSyncOperation = WriteImmediateData; pc.PostSyncOperation = WriteImmediateData;